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TM4C1294NCPDT: MOSC Single-Ended 25-MHz Oscillator Specification

Sebastian Ausserwoeger
Prodigy 220 points
Part Number: TM4C1294NCPDT

Hi,

we want to use the TM4C1294NCPDT in a new design, which utilizes the processors internal Ethernet PHY. For reasons of convenience we plan to source the processors main oscillator (MOSC) by means of an external clock oscillator with 3V3 CMOS output. Now, looking at Table 27-51 "MOSC Single-Ended 25-MHz Oscillator Specification" in the datasheet, all these requirements are usually easily fulfilled by an external clock oscillator with one exception - the maximum rise and fall time of 1ns. This requirement seems very stringent to me since virtually no clock oscillator on this planet can meet this requirement. Some parts might achieve rise and fall times as low as 2.5ns @ 15pF load - but that's it. I'm well aware that the oscillator output might be faster in reality due to the fact that trace and pad capacitance of the OSC0 input are probably well below 15pF.

An oscillator which we have often used in the past is MC3225Z25.0000C19XSH - but not in a design with TM4C129:

https://global.kyocera.com/prdct/electro/product/pdf/clock_mcz_xz_e.pdf

Anyway, I would appreciate it, if we could get some feedback on this topic.

Thanks and best regards,

Sebastian

  • +1
    TI__Guru 72500 points

    Sorry, that looks like an error in the datasheet. That parameter should be in the "min" column. The maximum slew rate for that input is 3.6 V/ns. That is to avoid accidentally activating an ESD protection structure. When they translated slew rate to rise time, they failed to move it from a max spec to a min spec.

    What is the true maximum rise time? It is given by the 40% to 60% duty cycle. The transition from 35% Vdd to 65% Vdd (or vice versa) should happen in less than 10% of the period, or 4 ns. 

  • 0
    Prodigy 220 points

    Hi Bob,

    thanks for the quick response. Your explanations sound very reasonable to me.

    Is this maximum slew rate requirement elsewhere to be found in the datasheet or does it apply to IOs other than the oscillator circuit? To be honest, I wasn't aware that such a requirement existed. Since the clock oscillator manufacturers usually only give information on max. rise and fall times in their datasheets, it's somewhat hard to predict if the oscillator circuit will be faster in the actual circuit and violate the slew rate limit. Also it is somewhat hard to verify actual slew rates by carrying out measurements, since an oscilloscope with really high bandwidth and probes which aren't loading the circuit too much would be needed.

    Did you ever experience customer issues with this slew rate limitation or is this rather a theoretical limit which is usually never exceeded in practical circuits?

    Thank you so much in advance.

    Best regards,

    Sebastian

  • 0 in reply to Sebastian Ausserwoeger
    TI__Guru 72500 points

    The only other pin with a maximum slew rate limit is VBAT. That is 0.7 V/us and is in the errata document as ELEC#02. The output transistors on the GPIO pins tends to protect those pins even when used as inputs only. I have never seen an issue on the TM4C129x devices but have had reports on other devices made in the same technology, but not on the oscillator input pin. 3V/ns is a very fast slew rate. I doubt you will find a crystal oscillator with that fast of a slew rate.

  • 0 in reply to Bob Crosby
    Prodigy 220 points

    Thanks again for the quick response. This is very helpful.