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TMS570LC4357: UART TX DMA

Kishore Bolisetti
Prodigy 185 points
Part Number: TMS570LC4357

Hello, I have configured transmit DMA function for one of the UART channel on the microcontroller. I am checking for DMA completion status by checking the HBC & BTC flags. I expect these flags to be set after successful transmission of requested bytes. But i am seeing, though there are bytes in the TX DMA buffer, the interface is setting these flags which is falsely indicating the operation is done. This is leading to corruption of the TX data when monitored on the receiving end.

Please let me know, what might be happening here.

Thanks,

Kishore

  • 0
    TI__Guru**** 197336 points

    Hello Kishore,

    When BTC interrupt is generated, is the number of transferred data equal to FRCNT*ELCNT? 

    Please try the example CCS project in this application note:

    www.ti.com/.../spna213.pdf

  • 0
    Prodigy 185 points

    Hi Wang, I am not using the DMA interrupts. This will have an impact to our processing cycles. Rather we would like to poll it, hence I am currently polling both HBC and BTC flags to get set to assume my previously initiated DMA transfer is successfully completed.

     

    But this is leaving few bytes to be transmitted still in the DMA buffers. Hence I am looking for some good way to poll the DMA transfer done status.

     

    Thanks,

    Kishore

  • 0 in reply to Kishore Bolisetti
    TI__Guru**** 197336 points

    The BTC flag is set only after the last element of the last frame has been transferred. The data in your DMA buffer (defined by DMA source address) should be transferred.

    If you want to transfer 8 bytes which are located in DMA buffer, when BTC flag is set, only 6 bytes are transmitted by the SCI module. The other 2 bytes are left in SCI registers (shift register and buffer register). 

    Simple workaround is to add additional 2 dummy chars in your DMA Buffer. 

  • 0 in reply to QJ Wang
    Prodigy 185 points

    Thanks Wang. I cannot transmit dummy bytes as the receiver will get impacted. Hence i added an additional wait to allow bytes to be transferred from shift register. I am able to resolve the problem. Thanks a lot.