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Original question:

TMS570LS3137: watchdoge cause the reset the cpu ,cpu condition

TMS570LS3137: if

whong zhao
Genius 4190 points

Part Number: TMS570LS3137

Hello

The NRES of TPS65381 is connected to TMS570 nPORRST,  if my program run a long time ,have some errors in program cause the external watchdoge reset the cup.

so if always reset the cpu，which is  problem. I want to prohibit reset the cpu .cpu is endless loop.

 How can we achieve this kind of scheme？

  • 0
    TI__Guru**** 199196 points

    Hi,

    To stop the reset, TMS570 needs to send the correct answer bytes calculated for the current question within the correct watchdog window and in the correct order. 

    Is there any problem with your SPI communication?

  • 0 in reply to QJ Wang
    Genius 4190 points

    Hello

    Maybe I didn’t describe it clearly.that is an assumption.If the communication line for tps65381 is faulty.I do not want the CPU to be reset always.

    so stop CPU reset

  • +1 in reply to whong zhao
    TI__Guru**** 199196 points

    Hi Whong,

    If the reset source is power-on reset, can you disable the TPS65381 watchdog and perform SPI self-test?

    Please be aware that maximum SPI speed supported by TPS65381 is 5 MHz (3.3 V system), and the minimum setup time nCS (tsucs) and hold time nCS (thcs) are 45 ns. The TMS570 SPI default settings (after reset) do NOT meet this requirement. You need to configure C2TDELAY and T2CDELAY in SPIDELAY register properly.

    TPS68381 requires that the SPI transfer inactive time (between 2 transfers) should be at least 788 ns. You have to set the WDELAY field in the SPI Data Format Register (SPIFMT0) in the TMS570 MCU side to meet this 788ns requirement.