TMS570LS3137-EP: MiBSPI word delay issue with DMA and WDEL

Are you able to determine from the scope pictures if the problem is in the data that comes from the slave, or in the ability of the master to read the data?

Hi Bob,

The slave expects the inter word delay of 75ns - 125ns from the master and as per the first scope image, the 'delay' of 118ns introduced by the master with WDEL = 0 makes slave to respond to the master. I am able to read the data packets from slave without any issue. Also, the status bits(24-31) in RxRAM reads 0.

The issue here is, even with WDEL = 0, I get 118ns approx. as inter word delay which is not intended. Since this delay meets the slave requirement, the slave responds correctly.

When WDEL  is set to '1' and WDELAY is just set to 0x01, the delay is 124ns approx.

When WDELAY = 0x02, the delay width is 136ns approx. 

When WDELAY = 0x03, the delay width is 149ns approx. 

The intent is software needs to control the inter word delay using WDEL and WDELAY values. So, when I use SPI without DMA, I set WDEL =1 and set WDELAY of 0x6 to meet the inter word delay requirement of 100ns(VCLK = 12.5ns).

However, with DMA and SPI, I am achieving this inter-word delay either with WDEL bit being set to '0' or WDELAY being set to 0x01 or sometimes with 0x02 with WDEL set to 1. And, If I set WDELAY to 0x03 or above, my slave responds incorrectly as expected as the delay is more than inter-word delay duration of 75ns to 125ns.

Is there any setting in DMA/SPI I need to look into to get rid of this 'additional' delay.

Please help.

Thanks,

Jai

OK, so I understand you have a special slave device that must receive a constant flow of data at 10M baud, with a CS high time of 75 to 125ns between each 16-bit transfer. You are able to achieve this with the MibSPI using interrupts and fine tuning the CS high time using WDELAY, but using DMA, the CS high time is significantly longer. Are there publicly available specs for this slave device?

Off hand, I do not know why using DMA would cause a longer delay. I will try to build my own test case and look at it tomorrow. Please correct any of my assumptions above if they are incorrect. 

Hi Bob,

OK, so I understand you have a special slave device that must receive a constant flow of data at 10M baud, with a CS high time of 75 to 125ns between each 16-bit transfer.
Yes, our board has FPGA which acts as slave device.

You are able to achieve this with the MibSPI using interrupts and fine tuning the CS high time using WDELAY,
Yes, we achieved this with the MibSPI (configured TG0 with buffer size as 128) but not using interrupts. We polled transfer group interrupt flag(bit-16, TGINTFLG) for end of transmission.

but using DMA, the CS high time is significantly longer.
Yes. 

Since the transfer size varies from 90 to 150(and even more in future), DMA and SPI were configured such that the element count is always '1' and frame count varies depending on transfer size (90 to 150). The BUFID(bit24 - bit30) in DMA0CTRL register is mapped to always write Tx Data into BUF0. Similarly always read Rx data from BUF0. So I transfer 'multiple' frames of 1 element each.

It appears using only 'one' buffer location in Multi buffer RAM to transfer data is making CS high time significantly longer. 

Updated info: Even if the buffer size is 4, then after  every 4th word, the CS high time is higher. The WDELAY is maintained between 4 words. It appears the DMA transfer using TG is creating delays no matter what the buffer size.

DMA configuration summary:
1. DMA CH-0 is mapped for SPI Transmission
2. DMA CH-0 element count is always '1' and frame count varies based on ICOUNTx value.
3. DMA CH-0 Read and write element size is 32 bit. Read address is SPI_TransmitBuffer[150] and write address is 0xFF0C0000.
4. DMA CH-1 is mapped for SPI reception
5. DMA CH-1 element count is 1 and frame count varies based on ICOUNTx value.
6. DMA CH-1 Read and write element size is 32 bit. Read address is 0xFF0C0200 and write address is SPI_ReceiveBuffer[150].
Note: I am intended to do 32-bit read and write transfer between SPI RAM and DMA channels.

SPI configuration summary:
1. Transfer group buffer size is configured as 1. TG0CTRL = 0x00700000, TG1CTRL = 0x00000100.
2. ONESHOT(bit-31, DMA0CTRL) is set to allow a block transfer of defined length (ICOUNTx + 1), mainly controlled by
the MibSPI.
3. BUFID(Bit24 - bit30) is mapped to 0 and Rx_DMA_Map is set to 2 while Tx_DMA_Map is set to 1 in DMA0CTRL register.
4. LARGE_COUNT(Bit-0, DMACNTLEN) is set to 1.
5. ICOUNT0(bit31 - 16) is configured periodically at 1ms based on packet size. Currently, it can vary from 90 to 150 words.
6. SPIFMT0 is configured as 0x06000710.
7. TxRAM control word is configured as 0x84EF. (BUFMODE is continuous, WDEL is set to 1 and chip select is 4 for MibSPI-3).

I have shared the implementation(functions SPI_Reconfig() and SPI_Periodic_transfer_trigger() for above configuration in my previous link for your reference.

e2e.ti.com/.../3649244

How do I transfer data of more than 128 words using MibSPI and DMA? What should be my DMA and SPI configuration to achieve this?

Please help.

Thanks,

Jai

Hi Bob, 

It appears SPI in compatibility mode works with DMA for my requirement. I could see slave timing requirements are met by looking into scope output. I will come back to you If I see any further problem with respect to timing.

Regarding TG, even if the buffer size is 4, then after  every 4th word, the CS high time is higher. The WDELAY is maintained between 4 words. It appears the DMA transfer using TG is creating delays no matter what the buffer size.

Thanks,

Jai