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TM4C1294KCPDT: What's the tolerance of System Clock Frequency with ADC Operation ?

Hideaki Matsumoto
Genius 9785 points

Part Number: TM4C1294KCPDT

Hi,

The customer is using TM4C1294KCPDT with 16MHz crystal to use ADC. They'd like to know what the tolerance of System Clock Frequency (Fsysadc) is. They found the following table in the datasheet, but there is no description about Min and Max. Could you tell them it ?

Thanks and regards,
Hideaki

  • 0
    TI__Guru 72500 points

    The ADC should be run with an ADC clock within the accuracy of the PIOSC, +/- 10%.

  • 0 in reply to Bob Crosby
    TI__Genius 9785 points

    Hi Bob,

    Thank you for your answer. We found the following data in the LM3S2U93 datasheet. It describes +/- 0.03% tolerance of Fsysad System Clock. How about TM4C1294KCPDT ?

    Regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Guru 72500 points

    That is a different part. 

  • 0 in reply to Bob Crosby
    TI__Genius 9785 points

    Bob,

    OK, I understood. +/- 10% which you mentioned means like below ?  It looks big tolerance.

    Fsysadc        Min 14.4        Nom 16        Max 17.6    MHz

    Regards,
    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Genius 9785 points

    Bob,

    Let me doublecheck, +/- 10% tolerance for 16MHz System clock frequency is applied to the both cases of PISOC (internal oscillator) and external clock source. Is this correct ?

    Regards,
    Hideaki 

  • 0 in reply to Hideaki Matsumoto
    TI__Guru 72500 points

    The ADC cannot tell the difference in clock source. Are you having problems with the ADC? If you see different results when running the ADC at 16MHz as opposed to 17.6MHz it is likely the sample time.

  • 0 in reply to Bob Crosby
    Mastermind 7170 points

    Hi Bob,

    I'm sorry to interrupt. I am the one who is in direct contact with the customer. Please allow me to supplement and reconfirm.

    Bob Crosby said:
    The ADC cannot tell the difference in clock source. Are you having problems with the ADC? If you see different results when running the ADC at 16MHz as opposed to 17.6MHz it is likely the sample time.

    Q:Am I correct in understanding that the +/-10% tolerance system clock frequency of 16MHz applies to both PISOC (internal oscillator) and MOSC (external clock source) because the ADC does not recognize the difference in clock sources?

    Currently, we are not experiencing any problems with the measurement results. Our customer is in the process of migrating from LM3S2U93 to TM4C1294KCPDT. In order to define the product specification document, they are asking for information on the tolerance of the system clock frequency (Fsysadc).

    In the LM3S2U93 datasheet, "25.8.5 Main Oscillator Specifications" states "If the ADC is used, the crystal reference must be 16 MHz ± .03% when the PLL is bypassed".

    The customer uses a 16 MHz crystal for the MOSC of the TM4C1294KCPDT. From "15.3.2.7 Module Clocking" in the TM4C1294KCPDT datasheet, I understand that the ADC clock source can be selected from three types: Divided PLL VCO, 16MHz PSOC, and MOSC.

    If there is another provision about the tolerance of the external crystal input to the MOSC when using the ADC, I would like to convey this.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru 72500 points
    O.H said:
    Q:Am I correct in understanding that the +/-10% tolerance system clock frequency of 16MHz applies to both PISOC (internal oscillator) and MOSC (external clock source) because the ADC does not recognize the difference in clock sources?

    It applies to PIOSC. With MOSC it can be greater. The limit is not the ADC, it is the specification of the PIOSC or the MOSC.

    O.H said:
    The customer uses a 16 MHz crystal for the MOSC of the TM4C1294KCPDT. From "15.3.2.7 Module Clocking" in the TM4C1294KCPDT datasheet, I understand that the ADC clock source can be selected from three types: Divided PLL VCO, 16MHz PSOC, and MOSC.

    That is correct.

    O.H said:
    If there is another provision about the tolerance of the external crystal input to the MOSC when using the ADC, I would like to convey this.

    Actually yes, when using the external crystal to generate the ADC clock it can be as fast as 25MHz. When using the PLL it can be as fast as 32MHz. See section 15.3.2.7 of the datasheet.

  • 0 in reply to Bob Crosby
    Mastermind 7170 points

    Hi Bob Crosby,

    Sorry for the late reply. It seems that the customer's question has been resolved. I appreciate your support!!

    Best regards,
    O.H