RM48L730: ECC for NAND FLash

Hello,

1. The EMIF module on Rm48x device can interface with NAND flash. You can use the available asynchronous memory chip selects (EMIF_nCS2, 3, 4) to access the external NAND flash memory. There are some constraints to keep in mind though:

- The EMIF does not control the "Write Protect" pin (WP#) on the NAND flash. This must be controlled using a general-purpose I/O pin and managed by software.
- The EMIF does not support NAND flashes that require the chip select to stay low during the data transfer time (tR). This must be controlled using a GIO pin and managed by software.

EMIF_DATA[7-0] to DQ[7-0]

EMIF_nWE to WE#

EMIF_nOE to RE#

GPIO to CE#,CLE, ALE, and WP#

GPIO to R/B

We don't have a ready example for you for interfacing a NAND flash memory using the EMIF on Hercules devices.

2. Yes, there are size limitation for async memory connected to EMIF. The NAND flash doesn't have address pins, and the address is defined through the commands. So I think the size of the NAND flash is not a issue. 

3. 

Wenhai Liao (6576188) said:

The ECC described in the datasheet is for On-chip Flash or external NAND FLash? The ECC for external NAND Flash is hardware ECC or software ECC? How many bits Error Detection and Error Correction it supported?

The ECC described in datasheet and TRM is only for the on-chip flash. The ECC of external NAND flash should be addressed by your SW.

Thank you for this information.

For the software ECC, it seems have a significantly impact on the NAND flash write/read speed, comparing to the hardware ECC solution. Also the CPU will be occupied to run the software ECC algorithm, so the CPU efficiency will be lower than using a hardware ECC. Is that right for my understanding? Thank you.