TMS570LC4357: UART RX DMA

I did a test using invalidate the data cache, so the memory region becomes coherent. The CPU can read the updated data from SRAM.

This is my example code:

1. the data buffer is allocated to .sharedRAM which is write-back and write allocated

2. the destination address of DMA transfer is in the section: .sharedRAM

3. Assigned data to rx_buffer[] first before DMA transfer

4. DMA transfer data from SCI RD register to rx_buffer[]

5. When DMA transfer is completed, invalidate the cache

6. check the memory content in CCS memory browser. The content is updated.

/* dma control packet configuration stack */
g_dmaCTRL g_dmaCTRLPKT;
uint32 DMA_Comp_Flag;

uint8 data_buff[128];

#pragma SET_DATA_SECTION(".sharedRAM")
uint8 rx_buffer[128]= {0}; /* receive buffer in sys ram */
#pragma SET_DATA_SECTION()

/* USER CODE END */

int main(void)
{
/* USER CODE BEGIN (3) */
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
uint8 src_addr_offset = 0; /* 0 for LE */
#else
uint8 src_addr_offset = 3; /* 3 for BE */
#endif

uint32 IDLECOUNT = 0, i;

_mpuInit_();

/* Reset the Flag to not Done*/
DMA_Comp_Flag = ~0x55AAD09E;

sciInit();

for(i=0; i<16; i++){
rx_buffer[i]= 0x55;
}

asm(" nop");

for(i=0; i<16; i++){
rx_buffer[i]= 0x5A;
}

/* Print header on SCI1 */
sci_printf(" Hercule SCI RX DMA Example - Version %\n\r");
sci_printf("**************************************\n\r\n\r");

/* Enable CPU Interrupts */
_enable_IRQ();

/* Enable DMA */
dmaEnable();

/* Enable Interrupt after reception of data */
dmaEnableInterrupt(DMA_CH0, BTC, DMA_INTA); /* DMA_CH0 is highest priority */

/* - Populate dma control packets structure */
g_dmaCTRLPKT.SADD = (uint32)(&(sciREG1->RD)) + src_addr_offset;
g_dmaCTRLPKT.DADD = (uint32)(&rx_buffer[0]);
g_dmaCTRLPKT.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT.ELCNT = 1; /* element count */
g_dmaCTRLPKT.FRCNT = 16; /* frame count */
g_dmaCTRLPKT.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT.ELSOFFSET = 0; /* element source offset */
g_dmaCTRLPKT.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT.FRSOFFSET = 0; /* frame source offset */
g_dmaCTRLPKT.PORTASGN = PORTB_READ_PORTA_WRITE;
g_dmaCTRLPKT.RDSIZE = ACCESS_8_BIT; /* read size */
g_dmaCTRLPKT.WRSIZE = ACCESS_8_BIT; /* write size */
g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT.ADDMODERD = ADDR_FIXED; /* address mode read */
g_dmaCTRLPKT.ADDMODEWR = ADDR_INC1; /* address mode write */
g_dmaCTRLPKT.AUTOINIT = AUTOINIT_OFF; /* autoinit */

/* - setting dma control packets for transmit */
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT);

/* assigning dma request: channel-0 with request line - 1 - RX*/
/* DMA Request 28 is for LIN ( SCI1) Receive */
/* Refer Data sheet - Default DMA Request Map section */
dmaReqAssign(DMA_CH0, DMA_REQ28);

/* setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH0, DMA_HW);

/* Enable RX DMA */
sciREG1->SETINT = (3 << 17);

sci_printf("sci dma rx Example \n\r");

//please input 16 chars from TeraTerm Terminal

/* Wait for the DMA interrupt ISR to set the Flag */
while(DMA_Comp_Flag != 0x55AAD09E){
IDLECOUNT++;
}
coreInvalidateICDCByAddress(0x0807F000, 0x1000);

asm(" nop");
/* USER CODE END */

return 0;
}