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TMS570LC4357: Issue in DMA registers configuration

Shivam Kakad
Prodigy 115 points

Part Number: TMS570LC4357

Hi team,

In our application for TMS570LC4357 processor we are using DMA engines where we are using the DMA channel numbers for establishing the communication over DMA. While implementing some of the DMA features, we have observed issues. 

1. To configure the triggering type we have observed that the registers are not getting updated as per the need. As per the TRM, HWCHENAS is used to configure the Hardware triggering whereas SWCHENAS register will be used for software triggering. But, it has been observed that HWCHENAS is getting configured properly but SWCHENAS register is not getting updated properly, even though we are on the privilege mode. Let me know how do we need to implement this logic so that, the required dma channel number we can configure for the required trigger type.

2. For configuring the dam channel priority also we would like to understand how we need to achieve this. As per the TRM, we have CHPRIOS and CHPRIOR registers for configuring the high and low priorities, but when we tried to configure the low it is not properly updating the required bits in that registers. Here also we would like understand how to achieve this so that we can configure the channel priority appropriately. For e.g. ch2 for low, ch5 for high, ch10 for high, ch15 for low.

Regards,

Shivam

  • 0
    TI__Guru**** 199286 points

    Hello Shivam,

    1. For DMA software request, if the DMA is enabled, the transfer is triggered by writing to SW channel enable set register (SWChnEnaSet). The bit is also cleared is immediately cleared after one frame transfer or one block transfer. You check if the bit in SWChnEnaSet register is set, please don't enable DMA before configuring this register.

    2. You can assign the channels in to high priority queue or low priority queue. Channel assigned to the high priority queue is serviced first. Each queue can be configured to use a fixed priority scheme or a rotating priority scheme.

    Writing 1 to the corresponding bit of CHPRIOS register is to assign this channel to the high priority queue, and Writing 1 to the corresponding bit of CHPRIOR register is to assign this channel to the low priority queue.

    ch5, ch10 -- high priority queue  ---- write 1 to bit 5 and bit 10 of CHPRIOS (0x420)

    ch2, ch15 -- low priority queue  ----  write 1 to bit 2 and bit 15 of CHPRIOR  (0x8004). Writing 1 will clear the corresponding bit in CHPRIOS register. 

    Be aware: reading 1 of both registers (CHPRIOS and CHPRIOR) indicates the corresponding channel is assigned to high priority queue. 

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Hi Wang,

    Thanks for your response. we got chance to retest on this today,.
    For the seconds scenario, we observed that whenever we are trying to configure the priority as low then it is actually resetting all the other earlier priorities sets. for e.g. if ChnPrioSet/ChnPrioRst is 0x00100200 and we attempted to write 0x00000001 to the ChnPrioRst register to configure the priority low then it is disturbing all other channels and getting read back as 0x00000000 as shown. Please help me, how can we configure the priorities high and low as per our need for the any of the required dma channel.

  • 0 in reply to Shivam Kakad
    Prodigy 115 points

    Somewhat similar thing i observed for the first scenario as well for configuring the channel priorities for the same channel. After configuring the channel 0 as high priority first and then low it is actually getting read back as both priorities are configured for that channel as shown below:

  • 0 in reply to Shivam Kakad
    TI__Guru**** 199286 points

    Writing 1 to bit 0 of ChnPrioRst register will only clear the bit 0 of ChnPrioSet, won't affect other bits. I just did couple test. Please make sure you write 0x00000001 rather than 0x00100201.

  • 0 in reply to QJ Wang
    Prodigy 115 points

    Sure wang. Thanks for response, i tried that for the priority registers, and it looks fine now. But, for the HW/SW triggering method i am still seeing the issue.

    I tried below mentioned test:

    dmaSetChEnable(DMA_CH20,DMA_HW); // CHANNEL 20 - HW
    dmaSetChEnable(DMA_CH0,DMA_HW); // CHANNEL 0 - HW
    dmaSetChEnable(DMA_CH20,DMA_SW); // CHANNEL 20 - SW
    dmaSetChEnable(DMA_CH10,DMA_HW); // CHANNEL 10 - HW
    dmaSetChEnable(DMA_CH20,DMA_HW); // CHANNEL 20 - HW
    dmaSetChEnable(DMA_CH0,DMA_SW); // CHANNEL 0 - SW

    I observed that for channel 0 or channel 20 it indicates both SW and HW triggerd method enabled, but in the last step for channel 0 we configured sw triggering and for channel 20 we configured for hw triggering but still it indicates the both trigger type is enabled.

    Please provide me help on how to tackle this situation:

  • 0 in reply to Shivam Kakad
    TI__Guru**** 199286 points

    Hello Shivam,

    Shivam Kakad said:
    but still it indicates the both trigger type is enabled.

    The DMA controller supports a mix of hardware request and software request on the same channel. But I don't suggest to use both HW and SW requests for the same DMA channel because it might result in an out of sync for DMA channel and peripheral.