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TMS570LC4357: Can I get the TI C compiler to generate UDIV/SDIV instructions?

Manuel Mohr
Prodigy 50 points

Part Number: TMS570LC4357

Hi,

according to the ARM Technical Reference Manual, the ARM Cortex R5F supports UDIV/SDIV instructions in both Thumb and ARM modes, beginning with Cortex-R5 r1p0.  See also here.

According to this post in this support forum here, the TMS570LC4357 uses Revision r1p2 of the Cortex R5F, so it should support UDIV/SDIV instructions in both Thumb and ARM modes.

However, I never see the TI C compiler (I tested version v20.2.1.LTS) actually emitting UDIV/SDIV instructions although I do set --silicon_version=7R5.

The compiler always calls __aeabi_idivmod.

To my understanding, it would be definitely safe to emit them in Thumb mode because all R5Fs support it (according to the ARM Technical Reference Manual).

In ARM mode, I can see that setting --silicon_version=7R5 is not specific enough to allow emitting UDIV/SDIV because I would also have to tell the compiler the revision of the core I'm targeting to be sure that the generated code can actually run.  However, I did not find documentation about such a switch in the manual.

Is there any way of getting the TI C compiler to actually emit those instructions in Thumb and/or ARM mode when I know that I'm using the TMS570 with a core that supports those instructions?

It would be great if someone could clarify this situation, thanks a lot in advance!

  • 0
    TI__Mastermind 49120 points

    See this thread for the cases when the compiler generates SDIV/UDIV instructions versus calling the helper function from the RTS library.

    https://e2e.ti.com/support/microcontrollers/hercules/f/hercules-safety-microcontrollers-forum/916999/compiler-tms570ls0432-division-and-abi-helper-functions-from-runtime-library

    I will let the compiler team comment on whether this is now supported in ARM ISA as well for Cortex R5F.

  • 0
    TI__Guru**** 253640 points

    When generating code for a Cortex-R5 CPU, the instructions SDIV and UDIV are available only in thumb mode.  Here is an example ...

    C:\working_directory>type file.c
int test_divide_instruction(int arg1, int arg2)
{
   return arg1 / arg2;
}

C:\working_directory>armcl -mv7r5 --code_state=16 --keep_asm file.c

C:\working_directory>findstr DIV file.asm
        SDIV      A1, A1, A2            ; [DPU_V7R4_PIPE0] |3|

    The first command shows the source code.  The second compiles it.  The third shows that the SDIV instruction is generated.  The compiler options are:

    • -mv7r5 : Selects the Cortex-R5 CPU
    • --code_state=16 : Thumb mode
    • --keep_asm : The assembly file generated by the compiler is normally deleted.  This option says to keep it instead.

    If you have an example that is similar, but does not generate an SDIV or UDIV instruction, please submit it by following the directions in the article How to Submit a Compiler Test Case.

    As for whether the SDIV and UDIV instructions are available in ARM mode ... The assembler issues an error if you try.  There is no mechanism to change that behavior.  

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    Prodigy 50 points

    Thank you for the elaborate reply.

    You are correct and my statement was wrong.  I can confirm that the TI C compiler emits UDIV/SIV in Thumb mode, and does not emit it in ARM mode.  I must have confused the output files from the two compiler runs.

    I had hoped that the TI compiler supported a switch like GCC's -march=armv7-r+noidiv to override the default behavior.

    Thanks!