I am setting up the SPI with the DMA.
I have set the SPIINT0 register's DMAREQENA to 1.
I have mapped the DMA controller to the SPIBUF register.
The TRM states:
The DMA request enable bit (DMA REQ EN) controls the assertion of requests to the DMA controller module. When a character is being transmitted or received, the SPI will signal the DMA via the DMA request signals, TX_DMA_REQ and RX_DMA_REQ. The DMA controller will then perform the required data transfer.
The SPI generates a request on the RX_DMA_REQ line each time the received data is copied to the SPIBUF.
I can find no reference to TX_DMA_REQ or RX_DMA_REQ in the TRM but from Table 4-3 in the TMS570 data sheet I assume that:
When SPI1 receives (i.e. SPIBUF is full) that a request is made to the DMA module on the zeroth DMA request line.
and
When SPI1 transmits (i.e. TXBUF is empty) that a request is made to the DMA module on the fisrt DMA request line.
Is this correct?
I notice that in TMS570 data sheet section 4.2:
The DMA controller on this device supports 16 channels and 32 request lines. Each of the 32 DMA
requests are assigned by default to one of the 32 available channels.
So are there 16 channels or 32 channels?
Steve
