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RM46L852: MibSPI Max Baud rate limitations

Part Number: RM46L852


What is the Max baudrate limitations for the MibSPI interface in slave mode with a VCLK of 96 MHz???

When looking in the Technical Reference Manual, it is stated that: "If the SPI is configured as slave, PRESCALEx does not need to be configured".
But in the datasheet under slave mode timing it is stated that:
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When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns
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So the prescale value has some saying in slave mode after all ????

If 20MHz SPI CLK is needed in slave mode, with a VCLK of 96 MHZ, the constraints above would indicate that prescale cannot be 0, but should be 4 ??

Anyway, I am having no luck getting it to work unless I reduce the baudrate to 10MHz. Is there some other limitations here ?

  • The SPICLK is driven by the SPI master. The prescale is not used by the SPI slave. The description in TRM is correct. For SPI slave, whatever the PRESCALE is configured, the input SPI clock should meet this requirement: period >= 40ns or the SPICLK frequency <= 25MHz 

    The maximum input frequency on the SPICLK pin when in slave mode is VCLK / 2.