Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 83 subscribers
  • Views 765 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LAUNCHXL-F28379D: Low speed clock for CPU1 and CPU2 of TMS320F28379D

Hang
Intellectual 755 points
Part Number: LAUNCHXL-F28379D
Other Parts Discussed in Thread: TMS320F28379D

Hi,

I have a question on the low speed clock settings of CPU1 and CPU2 for TMS320F28379D. 

In my application, I want to set the low speed clock for CPU1 to 50MHz (default), and 100MHz for CPU2. 

I learned that the LSPCLKDIV controls the low speed clock, and CLKSEM set the ownership. 

I leave everything in CPU1 as default. 

In CPU2 code in the main() function, I used the settings as below. 

EALLOW;
ClkCfgRegs.CLKSEM.bit.SEM = 2;            // Set ownership of LOSPCP to CPU2
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1; // Set LSPCLK equal to SYSCLK/2 = 100MHz
EDIS;

However, it didn't work. The LSPCLKDIV still showed me 0 value, in both pause and running state. 

Is there anything wrong in my settings?

Thank you very much!

Best,

Hang

  • +1
    TI__Guru** 113025 points

    Hi Hang,

    Hang said:
    In my application, I want to set the low speed clock for CPU1 to 50MHz (default), and 100MHz for CPU2. 

    Please note that there is only one configuration register for this which is applicable to CPU1 and CPU2 so if you change the value of this register, it'll change the LSPCLK frq for both CPU meaning at any given time LSPCLK frq for CPU1 and CPU2 subsystem will be same.

    Hang said:
    However, it didn't work. The LSPCLKDIV still showed me 0 value, in both pause and running state. 

    This is not correct. Semaphore register has KEY value also which need to be written along with SEM value hence you need to write full 32bit value. Also for CPU2 the value for SEM is 'b01 (1) not 2 so that need to be corrected as well.

    Please update the code like below let me know if you still face any issue.

    EALLOW;
    ClkCfgRegs.CLKSEM.all = 0xa5a50001;            // Set ownership of LOSPCP to CPU2
    ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1; // Set LSPCLK equal to SYSCLK/2 = 100MHz
    EDIS;

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 755 points

    Hi Vivek, 

    It works! Thank you so much!

    Best,

    Hang