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TMS320F28335: SYS/BIOS: Reduce low priority interrupt delay using Interrupt nesting and Sys Bios Preemption

stevenh
Guru 20045 points
Part Number: TMS320F28335


Hello,

I have this requirement:

1. A Capture port interrupt occurring on one TMS320F28335 needs to signal its occurrence to another TMS320F28335 using CAN bus communication.

2. The delay between the Capture port interrupt occurring and the other TMS320F28335 receiving and processing the information (in the CAN ISR) needs to be almost constant (maybe +/- several microseconds. I am not exactly sure yet what is the maximum acceptable non-constant delay).  

I believe this is possible without the Sys/Bios using interrupt nesting.  Is it possible with Sys/Bios? 

How would I code it in Sys/Bios to get the least amount of non-constant delay?

Thanks,
Stephen

  • 0
    TI__Guru 54195 points

    Where in the code are you sending the transmission? Do you have many other interrupts happening?

    Whitney

  • 0 in reply to Whitney Dewey
    Guru 20045 points

    Hello Whitney,

    The software is using 19 interrupt sources.  I might be able to move the code for 6 of the interrupt sources to a RTOS task.

    There are 5 interrupts that have higher priority than the Input Capture interrupts and there are 9 that have a higher priority than the CAN interrupts.

    However, to get minimum delay all of the ISRs need to allow nesting.

    Also, the Sys/Bios may have some part of its code that are not interruptible.  Is that correct?  Could you please describe those parts to me and give me some indication of what type of delay I can expect.

    Any other ideas would be appreciated.

    Thanks,

    Stephen

  • 0 in reply to Whitney Dewey
    Guru 20045 points

    Hello Whitney, 

    I missed answering one of your questions: "Where in the code are you sending the transmission?"

    The are two boards having the same TMS320F28335 processors.  A positive going edge of a signal will be captured by the capture port on one of the boards.  This will be signaled to the other board using the CAN bus.  The CAN ISR on the receiving board will process the information after it is received.

    I would like to reduce the amount of variable time delay to a minimum, i..e any variable delay from capturing the positive going edge to the processing completed in the CAN ISR.  The CAN delay will be constant, which is good.  The processing algorithm can adjust for a constant delay, however too much variable delay will cause issues.

    Stephen  

  • +1 in reply to stevenh
    TI__Guru 54195 points

    The SYS/BIOS benchmarks lists the interrupt latency which would include the maximum amount of time the kernel disables interrupts plus the Hwi dispatcher prologue.

    I do think nesting is going to be the best way to get a more consistent delay. Are you familiar with the masks that allow for testing in SYS/BIOS? There's some information about them on this page.

    Whitney

  • 0 in reply to Whitney Dewey
    Guru 20045 points

    Thanks.

    It looks like the interrupt latency is 242 cycles or 1.61us if the code is run in RAM (at 150MHz).  It could be significantly higher if run from Flash.

    Does the Sys/Bios Task switcher allow nesting? If not, does it also have a 242 cycles latency?

    Thanks for the information on Mask.

  • 0 in reply to stevenh
    TI__Guru 54195 points

    I'm not sure I would consider it nesting, but you can do things like Task_sleep or Task_yield to prompt a possible context switch between tasks. The benchmarks list cycle counts for some of those scenarios as well.

    There's also the minimal latency interrupt scenario mentioned in that thread with the mask info--basically plugging an ISR outside of the RTOS to avoid any of the latency added by the Hwi dispatcher.

    Whitney