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TMS320F28379D: CLB HLC register to counter write problem

Sergey Lepeshkin
Prodigy 10 points
Part Number: TMS320F28379D

Hi all!

I'm trying to create receiver for XY2-100 protocol (short description is in attached pdf) using CLB. I have faced problem with transferring data from one of HLC's register to counter using MOV instruction. It simply doesn't write value to counter. It seems to me to be somehow connected with counter's EVENT settings: when it set to shift left, write fails, but when it set to do nothing, write succeed.

To reproduce this problem in-vitro I've made simple counters and HLC setup:

1. Set COUNTER_1 and COUNTER_2 all inputs to constant zero, COUNTER_1 event to none and COUNTER_2 event to shift left:

2. Set HLC register R3 value to 1, event 0 input is boundary.in1 and program 0 is simply two mov's - R3 to C1 and R3 to C2.

3. Compile and run this test program. Feed step to corresponding microcontroller input, then suspend program in CCS and examine CLB debug registers:

COUNTER_1 value now is set to 1, but COUNTER_2 value is still 0.

So I suppose this problem is associated with counter's event setting. Am I right? Is there some workaround for this problem?

Anyway, my main question is: is it possible to create shift register with carry-in input in CLB?

P.S. Why I wish to use CLB for XY2-100 receiver is because there could be many identical data packets in series. I want to compare them using CLB and push only new data packets to CPU. Furthermore, there is parity field in packet and I want to check it in CLB too.

Documents_TD_XY2-100_R0703.pdf

  • 0
    TI__Guru 52020 points

    So to summarize when the COUNTER is shifting, HLC cannot update the COUNTER value through MOV? 

  • 0 in reply to Sergey Lepeshkin
    TI__Guru 52020 points

    Sergey,

    Let me check the HW real quick and see if this documented behavior or not.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Guru 52020 points

    This is expected and planned to go into the next revision of the TRM. With the COUNTER in LOAD mode/None mode, the HLC can do updates to the counter.

    In Add/sub or shift left/right mode, the HLC cannot do this.

    Nima

  • 0 in reply to Nima Eskandari
    Prodigy 10 points

    Hi Nima.

    Thank you for your answer. Now all become clear to me.

    Nothing important, but I have another question: who was expecting this behavior? TI's developers?

    Furthermore, there is some another controversies in SPRUHM8I, page 2797:

    Table 26-10. Instruction Format, column "3-Bit Destination" says: "Destination can be R0, R1, R2, R3, C0, C1, C2 Note that for ADD/SUB instructions, only R0 to R3 can be the destination.". But below in bullet list said:

    "ADD <Src> <Dest> This instruction performs an unsigned 32-bit addition. <Dest> = <Dest> + <Src>. Both <Src> and <Dest> can be R0, R1, R2, R3, C0, C1, or C2.

    SUB <Src> <Dest> This instruction performs an unsigned 32-bit subtraction. <Dest> = <Dest> - <Src> Both <Src> and <Dest> can be R0, R1, R2, R3, C0, C1, or C2."

    I've already submitted this problem through documentation feedback form, but I will leave this note here too.

  • 0 in reply to Sergey Lepeshkin
    TI__Guru 52020 points

    Yes, the TI apps team found that the documentation needed to be added for COUNTER LOAD mode vs HLC loads. We will certainly add it.

    The ADD/SUB dest. should only be R0 to R3. I will double check with design to ensure and add the limit to the dest in the ADD/SUB descriptions.