TMS320F28377S: some questions about CSFA and CSFB in epwm module

coke kou

Dear TI engineers,

I have some questions about CSFA and CSFB in AQCSFRC Register. When CSFA or CSFB equal 0 or 3, data sheet written 'Software forcing is disabled and has no effect'.

Does this mean the detail set by AQSFRC Register do not work? At this moment, what does voltage level (0 or 1) depend on?

Looking forward for your reply, thanks a lot!

over 5 years ago

0 coke kou over 5 years ago

Intellectual 310 points

anyone here?

0 Marlyn Rosales Castaneda20 over 5 years ago in reply to coke kou

TI__Mastermind 27200 points

Hi Coke,

When CSFA and/or CSFB are equal to 0 or 3 the EPWM outputs will not be forced to a certain state by the action qualifier and the continuous software force will not occur. If this is the case then the output is determined by the actions configured in the Action Qualifier (AQCTL register) and the rest of the epwm submodules like the deadband.

Best Regards,

Marlyn

0 coke kou over 5 years ago in reply to Marlyn Rosales Castaneda20

Intellectual 310 points

Hi,

Marlyn, thanks for your answer.

Now, I am studying three phase inverter. If I use Epwm1 to control one leg in two electrical level topology, I config epwm1A and epwm1B to reverse.

When the machine turn off, the program only set CSFA to 1 and DBCTL.bit.OUT_MODE to 0. I do not know very clear about why do not they set CSFB to 1. Even the first way could always turn off switch tube.

So, what am I missing?

Looking forward for your reply, thanks a lot!

0 Marlyn Rosales Castaneda20 over 5 years ago in reply to coke kou

TI__Mastermind 27200 points

Hi Coke,

I'll need to know more about how EPWMxA and EPWMxB are configured, would it be possible for you to attach the configuration code?

Best Regards,

Marlyn

0 coke kou over 5 years ago in reply to Marlyn Rosales Castaneda20

Intellectual 310 points

Hi,

Marlyn, here is the code.

ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;		// EPWMCLK =  PLLSYSCLK

	EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
	EPwm1Regs.TBCTL.bit.CLKDIV = 0;					
	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;	
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;			
	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;			
	EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;		
	EPwm1Regs.TBPRD = 6410;							
	EPwm1Regs.TBPHS.bit.TBPHS = 0;						
	EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;		
	EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;		
	EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;	
	EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; 	
	// duty = CMPA /TBPRD
	EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;			
	EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;		

	//EPwm1Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;	
	EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;			
	EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;	
	EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;		
	EPwm1Regs.DBFED.all = 300;						
	EPwm1Regs.DBRED.all = 300;						

	EPwm1Regs.ETSEL.bit.INTSEL = 1;  				
	EPwm1Regs.ETSEL.bit.INTEN = 1;   				
	EPwm1Regs.ETPS.bit.INTPRD = 1;   				

	EPwm1Regs.TZSEL.bit.CBC1 = TZ_ENABLE;			
	EPwm1Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;			
	EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;			
	EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;			
	EPwm1Regs.AQSFRC.bit.RLDCSF = 3;				


	EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;
	EPwm2Regs.TBCTL.bit.CLKDIV = 0;						
	EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;	
	EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;			
	EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;				
	EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;			
	EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;		
	EPwm2Regs.TBPRD = 6410;							
	EPwm2Regs.TBPHS.bit.TBPHS = 0;					
	EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;		
	EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;		
	EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; 	
	EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; 	
	EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;			        
	EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;				
	//EPwm2Regs.DBCTL.bit.MODE = DB_FULL_ENABLE;
	EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;			
	EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;	
	EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;		
	EPwm2Regs.DBFED.all = 300;						
	EPwm2Regs.DBRED.all = 300;						
	
	EPwm2Regs.ETSEL.bit.INTSEL = 2;  				
	EPwm2Regs.ETSEL.bit.INTEN = 1;   				
	EPwm2Regs.ETPS.bit.INTPRD = 1;   				 

	EPwm2Regs.TZSEL.bit.CBC1 = TZ_ENABLE;			
	EPwm2Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;			
	EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;			
	EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;			
	EPwm2Regs.AQSFRC.bit.RLDCSF = 3;

0 Marlyn Rosales Castaneda20 over 5 years ago in reply to coke kou

TI__Mastermind 27200 points

Hi Coke,

Is there a trip event happening when the machine is turned off? TZA and TZB are both configured to make EPWMxA and EPWMxB go low.

Also, I dont see any actions configured for EPWMxB only EPWMxA (AQCTLA), is this configured else where?

Best Regards,

Marlyn

0 coke kou over 5 years ago in reply to Marlyn Rosales Castaneda20

Intellectual 310 points

Hi,

Marlyn, when the machine wanted to turned off, the below code would be run.

                            EPwm1Regs.AQCSFRC.bit.CSFA = 1;EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;\
							EPwm2Regs.AQCSFRC.bit.CSFA = 1;EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;\
							EPwm3Regs.AQCSFRC.bit.CSFA = 1;EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;\
							EPwm4Regs.AQCSFRC.bit.CSFA = 1;EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;\
							EPwm5Regs.AQCSFRC.bit.CSFA = 1;EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;\
							EPwm6Regs.AQCSFRC.bit.CSFA = 1;EPwm6Regs.DBCTL.bit.OUT_MODE = DB_DISABLE

And I do not think any trip event happened when machine turned off normally.

TZA and TZB also could be configured to 0(High-impedance), and have no influence in result. It would only influence in dsp initial state.When machine wanted to work, the below code would be run.

                         	EPwm1Regs.AQCSFRC.bit.CSFA = 0;EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;\
							EPwm2Regs.AQCSFRC.bit.CSFA = 0;EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;\
							EPwm3Regs.AQCSFRC.bit.CSFA = 0;EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;\
							EPwm4Regs.AQCSFRC.bit.CSFA = 0;EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;\
							EPwm5Regs.AQCSFRC.bit.CSFA = 0;EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;\
							EPwm6Regs.AQCSFRC.bit.CSFA = 0;EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE

EPWMA and EPWMB are configure to correlation. I do not see the place where AQCTLB has been configured. when I connect the dsp to ccs,I could read the AQCTLB configured to 0 and AQCTLB2 configured to 5 for EPWM1 and EPWM2.

So, do you want any else information?

+1 Marlyn Rosales Castaneda20 over 5 years ago in reply to coke kou

TI__Mastermind 27200 points

Hi coke,

The reason why only the CSFA bit of the AQCSFRC register has to be set to 1 and not the CSFB is that EPWMxB is already low.

Giving some more context: EPWMxA is configured through the action qualifier to set on a CAU event and clear on a CAD event. EPWMxB is not configured to change states. However, the deadband submodule is configured to utilize the EPWMxA output coming from the action qualifier submodule as the input for both EPWMxA and EPWMxB (this is through the IN_MODE bits). Refer to the figure below where I have highlighted the path based on the code you provided. Once the OUT_MODE bit of the DBCTL register is set to be disabled, the EPWMxB output after the deadband submodule should be the same as the EPWMxB output that comes from the Action Qualifier submodule (always low). The CSFA bit will then drive EPWMxA low resulting in both outputs to be low.

Best Regards,

Marlyn

0 coke kou over 5 years ago in reply to Marlyn Rosales Castaneda20

Intellectual 310 points

Hi,

Marlyn,thanks for your explanation.

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TMS320F28377S: some questions about CSFA and CSFB in epwm module