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TMS320F28377S: Unexpected ePWM module behavior

David M. Alter
Guru 61235 points
Part Number: TMS320F28377S

C2000 Team,

I am using F28377S and getting unexpected behavior from the ePWM module.  I am configuring the ePWM2 for up/down count mode.

Unexpected behavior #1: If I preload the TBCTR with a non-zero value (e.g., 1), the timer does not start counting down at the PRD the first time.  It keeps counting up to 0xFFFF and then rolls over.  After that, I believe it responds correctly to period match.

Unexpected behavior #2: I have SOCB configured to trigger on period match.  But if I initialize with TBCTR=0, I get an SOCB trigger immediately upon enabling SOCB.  The TBCTR is still showing zero.

I have code that illustrates the problem, and would like to WebEx with someone.  Please let me know.

Regards

David

  • 0
    TI__Genius 15260 points
    Hi David,

    My first thought on #1 is this is likely the TBPRD hasn't been loaded from the shadow register. When the counter overflows it is likely triggering the shadow to active load.

    For #2 I would have to take a look at the code. Could you send it to me offline, and we can discuss about the support moving forward as well.

    Regards,
    Kris
  • 0 in reply to Kris Parrent
    TI__Guru 61235 points

    Hi Kris,

    The TBPRD shadowing was the problem for both issues in fact.  For the second issue, the initial active PRD register must be zero.  Therefore, SOCA triggered on ZRO, and SOCB correctly triggered on PRD, both at the same time.

    The way to get around this is to set immediate reload of PRD register in TBCTL register, write the initial PRD value, and then set TBCTL to reload of PRD on ZRO match for normal (typical) operation.  For example:

     EPwm2Regs.TBCTL.all = 0x003B;   // Configure timer control register
    // bit 15-14     00:     FREE/SOFT, emu halt: 11 = ignore, 00 = stop immediately
    // bit 13        0:      PHSDIR, 0 = count down after sync event
    // bit 12-10     000:    CLKDIV, 000 => TBCLK = HSPCLK/1
    // bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = EPWMCLK/1
    // bit 6         0:      SWFSYNC, 0 = no software sync produced
    // bit 5-4       11:     SYNCOSEL, 11 = sync-out disabled
    // bit 3         1:      PRDLD, 0 = reload PRD on ZRO, 1 = immediate reload on access
    // bit 2         0:      PHSEN, 0 = phase control disabled
    // bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)

     EPwm2Regs.TBCTR = 0x0000;    // Clear timer counter

     EPwm2Regs.TBPRD = ADC_SAMPLE_PERIOD; // Set timer period
     EPwm2Regs.TBCTL.bit.PRDLD = 0;       // Reload PRD on ZRO

    I will close this thread.  Thanks!

    - David

  • 0 in reply to David M. Alter
    TI__Genius 15260 points
    David,

    Great. I'm glad we could help.

    Kris
  • 0 in reply to Kris Parrent
    TI__Guru 61235 points
    Well, my workaround doesn't quite do it. Seems it is easy to miss the first period and wrap around. I am still investigating....

    - David
  • 0 in reply to David M. Alter
    TI__Genius 15260 points

    David,

    What do you have the shadow-active load event setup as? Could you temporarily use PHSEN and do a SWFSYNC for the initial shadow to active copy?

    EDIT: Sorry- I see you posted that it PRDLD = 0 which is load the shadow TBPRD on CTR=0.  This makes sense for your initial problem #1, but I'm surprised that for #2 if you are starting at TBCTR=0 that it's not immediately loading the shadow register.  Am I understanding #2 correctly?


    Regards,
    Kris

  • 0 in reply to Kris Parrent
    TI__Guru 61235 points

    Hi Kris,

    I found that it needs to be done this way:

        EPwm2Regs.TBCTL.all = 0x003B;   // Configure timer control register
    // bit 15-14     00:     FREE/SOFT, emu halt: 11 = ignore, 00 = stop immediately
    // bit 13        0:      PHSDIR, 0 = count down after sync event
    // bit 12-10     000:    CLKDIV, 000 => TBCLK = HSPCLK/1
    // bit 9-7       000:    HSPCLKDIV, 000 => HSPCLK = EPWMCLK/1
    // bit 6         0:      SWFSYNC, 0 = no software sync produced
    // bit 5-4       11:     SYNCOSEL, 11 = sync-out disabled
    // bit 3         1:      PRDLD, 0 = reload PRD on: 0 = ZRO, 1 = immediate on access
    // bit 2         0:      PHSEN, 0 = phase control disabled
    // bit 1-0       11:     CTRMODE, 11 = timer stopped (disabled)

        EPwm2Regs.TBPRD = ADC_SAMPLE_PERIOD; // Set timer period (active register)
        EPwm2Regs.TBCTL.bit.PRDLD = 0;          // Reload active PRD on ZRO
        EPwm2Regs.TBPRD = ADC_SAMPLE_PERIOD;    // Set timer period (shadow register)

    It seems that if the reload is configured for immediate, it doesn't actually load the shadow PRD.  The design must be an either shadow or active, and not a pass through the shadow to the active.  So, you have to do a second write to load the shadow after configuring for shadow mode.  This seems to do the trick.

    Regards,

    David