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TMS320F28388D: TMS320F28388D -> Connectivity Manager MCAN CAN clock 20 MHz, 40 MHz or 80 MHz

Manuel Karch
Prodigy 10 points
Part Number: TMS320F28388D

Hello Support Team

We use the MCAN interface with CAN-FD. According to "CiA 601-2" specification CAN clocks of 20 MHz, 40 MHz or 80 MHz should be used.

At the moment we are running the processor with 125MHz and there is no integer divider to get the mentioned CAN clocks.

For a test software we set the "MCAN Auxpll" to 120MHz and the "MCANCLKDIV" to 2 which means divide by 3.

Then we got the 40MHz, for the MCAN Clock, that worked.

The question is now is there another way than to downclock the microcontroller by 5MHz.

With the following conditions:

         - The CPU28 CPU1/2 must still run with 200MHz.

         -The AUXCLKIN (GPIO133) can not be used, because the hardware is already final.

 

Thx

  • 0
    TI__Guru* 95315 points

    What is the input clock to the device?

    I am not familiar with "CiA 601-2" specification, but I’d like to know why it mandates CAN clocks of 20 MHz, 40 MHz or 80 MHz. Isn’t the final bit-rate that is important?

  • 0 in reply to Hareesh Janakiraman
    Prodigy 10 points

    The input clock is 16MHz.
    In the case of CAN-FD (and two Bitrates: arbitration and dataphase ) all CAN nodes, on the bus, should have the same or a similar bit-timing setting. Because the similar sample points are quite important.

    This is published in a lot of documents and specifications. 
    (I have made, the last weeks, the same experiences on my test setup)

  • 0 in reply to Manuel Karch
    TI__Guru* 95315 points

    Is using 20 MHz input clock an option?

    For the bit-timing, have you determined the desired bit-rate and sampling-point cannot be achieved with your existing hardware configuration?

  • 0 in reply to Hareesh Janakiraman
    TI__Guru* 95315 points

    Can you please clarify what bit-rate and sampling point you are trying to achieve? I’d like to ascertain if the desired parameters can be achieved with CAN clocks other than 20, 40 or 80 MHz. Should even the time-quanta be identical across the network? 

    With the existing design, the following configuration is the best option: 

    (16/2)*(50/2) = 200 MHz (for SYSPLL) 

    Through AUXPLL:

    (16/2) * (30/2) for CMCLK (Yes, it is only 120 MHz)

    (16/2) * (30/3) for MCAN bit-clock

  • 0 in reply to Hareesh Janakiraman
    TI__Guru* 95315 points

    Just to clarify, AUXPLLRAWCLK is 240MHz i.e. (16/2)*(30/1).

     

    Use CMCLKDIV=2, to get CMCLK=120Mhz,

    And MCANCLKDIV=3, to get MCANBITCLK=80MHz