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Hi TI ,
Wanted to know how exact purposes of CLB Tile Clock and CLB Register Clock , can you please little more information on its usages and purposes inside CLB module ?
Thanks
Abhishek
The TILE clock which is used ONLY to clock the logic inside your CLB TILE (where your custom logic is), has speed limitations. For example for this device if TILE clock is past 150MHz, the correctness of the logic is not guaranteed. If the TILE clock is within 100 to 150 MHz, PIPELINE mode must be enabled. If the TILE clock is at 100 MHz or below, the TILE operates normally even without PIPELINE mode.
The TILE clock is just for the TILE logic.
The register clock is the clock that controls the actual peripheral and its registers in the device. Similar to any other peripheral.
Nima
Thanks Nima for the reply ,
Just confirming PIPELINE mode need not to be enabled if Register Clock alone exceeds 150Mhz right ?
Thanks
Abhishek
Just confirming PIPELINE mode need not to be enabled if Register Clock alone exceeds 150Mhz right
TILE CLOCK! TILE clock exceeds 100MHz you have to enable PIPELINE mode. TILE CLOCK can go up to 150MHz max!
Nima