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TMS320F28388D: Output association between different tiles of CLB

user6101616
Intellectual 320 points
Part Number: TMS320F28388D

Hi,

I route 3 ePMW input corresponding to tile 1 to tile3, and output different duty cycle respectively：

 CLB_configGlobalInputMux(CLB1_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM1A);
 CLB_configGlobalInputMux(CLB1_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM1B); 

   GPIO_setPinConfig(GPIO_145_EPWM1A);
    GPIO_setDirectionMode(145, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(145, GPIO_PIN_TYPE_STD);
    
    GPIO_setPinConfig(GPIO_146_EPWM1B);
    GPIO_setDirectionMode(146, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(146, GPIO_PIN_TYPE_STD);

    CLB_setGPREG(CLB1_BASE, 0);
    CLB_setOutputMask(CLB1_BASE, 1 << 0 | 1 << 2, true);

 CLB_configGlobalInputMux(CLB2_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM2A);
 CLB_configGlobalInputMux(CLB2_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM2B);

    GPIO_setPinConfig(GPIO_147_EPWM2A);
    GPIO_setDirectionMode(147, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(147, GPIO_PIN_TYPE_STD);
   
    GPIO_setPinConfig(GPIO_148_EPWM2B);
    GPIO_setDirectionMode(148, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(148, GPIO_PIN_TYPE_STD);

    CLB_setGPREG(CLB2_BASE, 0);
    CLB_setOutputMask(CLB2_BASE, 1 << 0 | 1 << 2, true);

  CLB_configGlobalInputMux(CLB3_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM3A);
  CLB_configGlobalInputMux(CLB3_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM3B);

    GPIO_setPinConfig(GPIO_149_EPWM3A);
    GPIO_setDirectionMode(149, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(149, GPIO_PIN_TYPE_STD);
  
    GPIO_setPinConfig(GPIO_150_EPWM3B);
    GPIO_setDirectionMode(150, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(150, GPIO_PIN_TYPE_STD);

    CLB_setGPREG(CLB3_BASE, 0);
    CLB_setOutputMask(CLB3_BASE, 1 << 0 | 1 << 2, true);

But I found that if the PWM output logic of tile1 was pulled low by TILE1's logic. at the same time, the PWM output of tile2 and tile3 is pulled low, which is very strange, I don't know why?

Hope for your response, thank you!

The logic is as follow:

  • 0
    TI__Guru 52020 points

    There must be an error in your input setup.

    I think what is happening is that for some reasong TILE2 and TILE3 are still using EPWM1 signals.

    Here is what must be checked, 

    1. Check your LOCAL input mux setting, make sure it is set to GLOBAL.

    2. Check to make sure that GPREG is not used as the input instead of the LOCAL and GLOBAL mux.

    3. Change the logic for TILE2 and TILE3 to see if pulling their outputs low affects EPWM1

    Overall, it seems that EPWM1 is used as the input for TILE2 and TILE3 so when you pull EPWM1 low in the logic of TILE1, it affects the other TILEs.

    Let me know what you find!

    Nima

  • 0 in reply to Nima Eskandari
    Intellectual 320 points

    Hi，

    The TILE2/3 output is the duty cycle of pwm2AB / 3AB's configuration, but if the TILE1 's output is blocked, the output of TILE2 and TILE3 is abnormal

    And I checked the LOCAL input mux is set to GLOBAL ,    meanwhile the GPREG is not used

    I go on finding what happened.

    And the ".c" code is as follow:

    Clb_Cfg.c
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    /*
    * Clb_Cfg.c
    *
    * Created on: 2020��3��10��
    * Author: lizheng
    */
    #include "CLb_Cfg.h"
    #include "clb.h"
    #include "device.h"
    void Clb_Ini(void)
    {
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0011); /*CLB1 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0111); /*CLB2 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0211); /*CLB3 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0311); /*CLB4 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0411); /*CLB5 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0511); /*CLB6 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0611); /*CLB7 clock*/
    SysCtl_enablePeripheral((SysCtl_PeripheralPCLOCKCR)0x0711); /*CLB8 clock*/
    GPIO_setPinConfig(GPIO_76_GPIO76);
    GPIO_setDirectionMode(76, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(76, GPIO_PIN_TYPE_PULLUP);
    //
    // Configure Input-XBAR INPUT76
    //
    XBAR_setInputPin(XBAR_INPUT_BASE, XBAR_INPUT1, 76);
    //
    // Configure CLB-XBAR AUXSIG0 as INPUT1
    //
    XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX01_INPUTXBAR1);
    XBAR_enableCLBMux(XBAR_AUXSIG0, XBAR_MUX01);
    CLB_enableCLB(CLB1_BASE);
    initTILE1(CLB1_BASE);
    CLB_enableCLB(CLB2_BASE);
    initTILE1(CLB2_BASE);
    CLB_enableCLB(CLB3_BASE);
    initTILE1(CLB3_BASE);
    //CLB_enableCLB(CLB4_BASE);
    //initTILE1(CLB4_BASE);
    //
    // CLB1 Configure
    //
    //
    // Select Global input instead of local input for all CLB1 IN
    //
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN2, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN5, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN6, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN7, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to user6101616
    TI__Guru 52020 points

    Are your ePWMs linked to each other?

  • 0 in reply to Nima Eskandari
    Intellectual 320 points

    No, Independent PWM 

  • 0 in reply to user6101616
    TI__Guru 52020 points

    Were you able to find out what was causing this? It is most definitely a setup issue.

  • 0 in reply to Nima Eskandari
    Intellectual 320 points

    Hi Nima,

    We analyze the independence of three PWM channels and find that the three PWM channels use the same time benchmark, but the input and output of PWM channels are controlled independently. But the root cause has not been found

  • 0 in reply to user6101616
    TI__Guru 52020 points

    Can you test each of the tiles independently? Take out the other 2 tiles and test only 1 tile at a time? 

  • 0 in reply to Nima Eskandari
    Intellectual 320 points

    Hi Nima,

    I have resolved the issue yesterday. During the ePWM configuration, the pwm-bar's input are routed to one channel.

    Thank you.