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Original question:
Hi! I would like to combine the CLA Program RAM with the CLA Data RAM1 (L3 DPSARAM with the L2 DPSARAM). There are no issues with compilation after restructuring and combining L2 and L3. However, unable to initialize the CLA and so the CLA is unable to run.
I initialize the CLA with the following code:
memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize);
memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadSize);
When I set a "__mdebugstop()" breakpoint within my interrupt in the CLA, the breakpoint is unable to be reached. I tested with the original .cmd file pre-restructuring and had no issues. So my question is, is it possible to combine L2 and L3? If so, how do I go about this. Thank you for your help.
My .cmd file for reference
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
// RAML3->CLA Program space
RAML23 : origin = 0x008C00, length = 0x001400 /* on-chip RAM block L3 */
RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHFE : origin = 0x3E0000, length = 0x008000 /* on-chip FLASH */
// FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
//==============CPU Space/ CLA DataRAM space=======================================//
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
// RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
//=================================================================================//
RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */
RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */
RAML78 : origin = 0x010000, length = 0x004000 /* on-chip RAM block L7 */
// RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHFE, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN, PAGE = 0
/*
Cla1Prog : LOAD = FLASHA,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
*/
//#ifdef __TI_COMPILER_VERSION__
// #if __TI_COMPILER_VERSION__ >= 15009000
// .TI.ramfunc : {} LOAD = FLASHD,
// RUN = RAML0,
// LOAD_START(_RamfuncsLoadStart),
// LOAD_END(_RamfuncsLoadEnd),
// RUN_START(_RamfuncsRunStart),
// PAGE = 0
// #else
// ramfuncs : LOAD = FLASHD,
// RUN = RAML0,
// LOAD_START(_RamfuncsLoadStart),
// LOAD_END(_RamfuncsLoadEnd),
// RUN_START(_RamfuncsRunStart),
// PAGE = 0
// #endif
// #endif
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > RAML4, PAGE = 1
.esysmem : > RAMM1, PAGE = 1
.scratchpad : > RAML1, PAGE = 1
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHC, PAGE = 0
.switch : > FLASHA, PAGE = 0
.scratchpad : > RAML1, PAGE = 1
snapshot_buffer : > RAML78, PAGE = 1
graph_buffer : > RAML5, PAGE = 1
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
ClaToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 /* Link to PF0 - CLA Message RAM */
CpuToClaMsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1 /* Link to PF0 - CLA Message RAM */
/* Section Cla1Prog used by file Cla.c */
Cla1Prog : LOAD = FLASHH, PAGE = 0 /* Load to flash, run from CLA Prog RAM */
RUN_START(_Cla1Prog_Start)
RUN = RAML23, PAGE = 0
LOAD_START(_Cla1funcsLoadStart),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart)
CLA1mathTables : LOAD = FLASHC, PAGE = 1
RUN = RAML1, PAGE = 1
LOAD_START(_CLA1mathTablesLoadStart),
LOAD_END(_CLA1mathTablesLoadEnd),
LOAD_SIZE(_CLA1mathTablesLoadSize),
RUN_START(_CLA1mathTablesRunStart)
ramfuncs : LOAD = FLASHD, PAGE = 0
RUN = RAML6 , PAGE = 0
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart)
Cla1DataRam1 : > RAML0, PAGE = 1
/*
DMARAML5 : > RAML5, PAGE = 1
DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1
DMARAML8 : > RAML8, PAGE = 1
*/
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
/* Allocate IQ math areas: */
IQmath : > FLASHA, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
/*
//===========================================================================
// End of file.
