TMS320F28388D: C28xx_CPU1: Trouble Removing Breakpoint with the Action "Remain Halted"

We have a new board with the C28x on it.  Previous revisions of the board worked fine, but the new one does not seem to connect.

When running CCS debugger we see the following message.

Can anyone suggest what may be at fault, or even tell us what is at least working?  Ie, JTAG is fine, MCU core is up....  

Suggestions on debugging would be really helpful.

Please see full details below:

C28xx_CPU1: Trouble Removing Breakpoint with the Action "Remain Halted" at 0xd148: (Error -1066 @ 0xD148) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 9.3.0.00042)
C28xx_CPU1: Error executing PLL configuration algorithm. Operation cancelled. (0x0)
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: GEL: File: C:\Users\hduon\OneDrive - Legend Power\code\gen3_dsp\gen3_pjt\Release\gen3_release.out: Load failed.
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0xd058: (Error -1066 @ 0xD058) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 9.3.0.00042)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint
C28xx_CPU1: Error occurred during flash operation: Timed out waiting for target to halt while executing pwrite_en.alg
C28xx_CPU1: Error occurred during flash operation: Cannot disable hardware breakpoint while the target is halted. Halt the target and try again

What has been checked:

- All 3.3V and 1.2V sources are present.

- XRS is 3.3v

- X1 has 20MHz signal from oscillator

Full console log:

C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
CM is out of reset and configured to wait boot.
(If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
CM is out of reset and configured to wait boot.
(If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
CM is out of reset and configured to wait boot.
(If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: Trouble Removing Breakpoint with the Action "Remain Halted" at 0xd148: (Error -1066 @ 0xD148) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 9.3.0.00042)
C28xx_CPU1: Error executing PLL configuration algorithm. Operation cancelled. (0x0)
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: GEL: File: C:\Users\hduon\OneDrive - Legend Power\code\gen3_dsp\gen3_pjt\Release\gen3_release.out: Load failed.
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0xd058: (Error -1066 @ 0xD058) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 9.3.0.00042)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint
C28xx_CPU1: Error occurred during flash operation: Timed out waiting for target to halt while executing pwrite_en.alg
C28xx_CPU1: Error occurred during flash operation: Cannot disable hardware breakpoint while the target is halted. Halt the target and try again

Test Connection Log:

[Start: Texas Instruments XDS100v2 USB Debug Probe_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

C:\Users\hduon\AppData\Local\TEXASI~1\CCS\
ccs1030\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Jan 31 2021'.
The library build time was '20:08:09'.
The library package version is '9.3.0.00042'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v2 USB Debug Probe_0]