This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388D: Interference details for accessing the Global shared RAM

Part Number: TMS320F28388D

Hello TI,

Scenario1: If CPU1 is accessing GS0, and CPU2 is accessing GS1 at the same time would there be any interference?

Scenario2: If CPU1 is accessing GS0, and CPU2 is accessing GS0 at the same time would there be any interference?

Thanks,

Niharika

  • Hi,

    Scenario1: If CPU1 is accessing GS0, and CPU2 is accessing GS1 at the same time would there be any interference?

    No, there will be no interference because each RAM block has it's own wrapper and arbitration logic.

    Scenario2: If CPU1 is accessing GS0, and CPU2 is accessing GS0 at the same time would there be any interference?

    Yes, in this case access from both the CPU will be arbitrated in round-robin scheme. Please note that only one CPU, which has ownership of that RAM block, will have write/fetch access. Only read access is allowed from both CPU.

    Regards,

    Vivek Singh