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TMS320F28379D: C2000ware example gives "Multiple debuggable cores detected" error when loading .out file to flash

Part Number: TMS320F28379D
Other Parts Discussed in Thread: LAUNCHXL-F28379D, C2000WARE

Symptom is very similar to the thread by Ian Cartwright, from which I branched to make this thread. That was one of only two threads that mention this error message for a Delfino dual core target. His case was complicated by other issues like building from MATLAB. The error message was never resolved. A message at the end said a new thread was created to continue pursuing the topic, but there is no link to that thread.

My case is relatively simple. The target is a LaunchXL-F28379D. The environment is C2000ware v3.4.0, CCS v10.4, with compiler version 20.2.5 LTS. 

I am trying to run the adc_soc_epwm example project for CPU1 only from C2000ware for the F28379D. At first I got the error when either loading to RAM or FLASH. Somehow I managed to get the load to RAM from Run/Debug to work. Run/Load to FLASH still gives the error. 

I have several related questions: 

1) When the load operation is attempted the first time, an early step displays a window to select CPU1, CPU2 or both. Since the project is for CPU1 only, is the correct choice to uncheck CPU2 and leave CPU1 checked?

2) That CPU selection window only appears on the first attempt. On subsequent attempts, it is never shown again, so I never have a chance to go back and attempt another configuration. Why is that? Is there a way to make that window appear again, so a different choice can be entered?

I have been unable to find information on that error message in any TI documentation. It would be helpful if there is are resource that describes what it means, and what techniques can be used to resolve it. 

I can send a ZIP file of my project if that would be helpful.