TMS320F28388D: Bus Interconnect scheme on Peripheral Bridge

Part Number: TMS320F28388D

Hello Experts,

In the TRM, there is no clear description of the bus interconnects and the logic inside the Peripheral Frame (Bridge). Detailed Interconnect scheme of the Peripheral frame is necessary to prove why there is no arbitration between the Peripheral access within the same Peripheral Frame between CPU1 and CPU2. This is important for the multicore safety assessment.

I have prepared a high level bus interconnect diagram with the Mux selection based on CPUSEL for Peripheral Frame 9 of TMS320F28388D. Is this diagram good enough to explain why there is no arbitration between the both CPUs access?

Best Regards

Amulrass V