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Original question:

TMS320F28388D: LSPCLK configuration

TMS320F28388D: Could not read EPWM1 module's TBCTR register value from CPU2

Amulrass Vazhumuni
Intellectual 435 points

Part Number: TMS320F28388D

Hello,

I am able to read EPwm1Regs.TBCTR (up-down counter) from CPU1 but the same register is read as zero from CPU2. All other EPWM1 registers also shows zero in CPU2 register window of CCS.

EPWM1 clock is supplied by CPU1 (CPUSEL0.EPWM1 = 1). So, will this mean that, only CPU1 can read the EPWM1 registers? or something else I need to configure in the software?

Best Regards

Amulrass V

  • 0
    TI__Guru** 116081 points

    Hi,

    Access are provided based on CPUSEL value so if you have CPUSEL value for EPWM1 to give access from CPU1 then CPU2 will not have access. You need to change the value of CPUSEL to give access to CPU2.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 435 points

    Hi Vivek,

    It is interesting to see, that access to shared peripherals are provided on the basis of the CPUSEL value. Is this true for all other shared peripherals as well?

    I know most other multicore platforms (like PPC) don't restrict any CPU's access to the shared peripherals even though only one CPU can control or use the peripheral at any point of time. It would be severely limiting the multicore application programs, as in my case.

    I need to access the EPWM1 registers from both CPUs and I don't want to change the CPUSEL at runtime. Is there any workaround for this issue? 

    Best Regards

    Amulrass 

  • 0 in reply to Amulrass Vazhumuni
    Intellectual 435 points

    Hi,

    One more thing. Does modifying CPUSEL at runtime won't cause any glitches to the input clock to EPWM module?

    Best Regards

    Amulrass V

  • 0 in reply to Amulrass Vazhumuni
    TI__Guru** 116081 points

    Hi,

     Is this true for all other shared peripherals as well?

    Yes, it's same for all peripherals which are controlled by CPUSEL.

     I know most other multicore platforms (like PPC) don't restrict any CPU's access to the shared peripherals even though only one CPU can control or use the peripheral at any point of time. It would be severely limiting the multicore application programs, as in my case.

    You are right but in that case arbitration is done between access and that makes it hard for control loop where timing is critical.

     I need to access the EPWM1 registers from both CPUs and I don't want to change the CPUSEL at runtime. Is there any workaround for this issue?

    You need to access same EPWM module from both CPU ? If yes, then that is not possible in current architecture. You have to pass the information via IPC only. We have multiple EPWM module and you can assign some to CPU1 and other to CPU2 if that helps.

     One more thing. Does modifying CPUSEL at runtime won't cause any glitches to the input clock to EPWM module?

    You need to disable the clock to EPWM module and make sure there is no pending access form CPU to EPWM module to switch the CPUSEL else it may cause a glitch.

    Regards,

    Vivek Singh 

  • 0 in reply to Vivek Singh
    Intellectual 435 points

    Hi Vivek,

    I have a point on your above reply:

    "You are right but in that case arbitration is done between access and that makes it hard for control loop where timing is critical".

    For example, EPWM1 module is assigned to CPU1 and EPWM2 module is assigned to CPU2 via CPUSEL. I believe arbitration takes place between the CPU1 access and CPU2 access, as all the EPWM modules share the common bridge. Also Arbitration between CPU1 and CPU2 access takes place between the different peripherals which are connected to the same bridge.

    Am I missing something here?

    Best Regards

    Amulrass V

  • +1 in reply to Amulrass Vazhumuni
    TI__Guru** 116081 points

    Hi,

     For example, EPWM1 module is assigned to CPU1 and EPWM2 module is assigned to CPU2 via CPUSEL. I believe arbitration takes place between the CPU1 access and CPU2 access, as all the EPWM modules share the common bridge. Also Arbitration between CPU1 and CPU2 access takes place between the different peripherals which are connected to the same bridge.

    No, in that case arbitration does not comes into picture because CPU1 and CPU2 are different bus. Bridge is combination of mux and other logic and does not takes care of arbitration.

    Regards,

    Vivek Singh