Hello Team,
I'd like to ask a question about the power-up sequence. In SPRSP14B in 5.8.1 this paragraph:
"VDDIO and VDDA Requirements: The 3.3-V supplies VDDIO and VDDA should be powered up together
and kept within 0.3 V of each other during functional operation."
I'd like to ask how strict is this requirement. I mean can VDDIO ramps up first and VDDA rise 2ms later or both must be tight together all the time? Is it dangerous for the MCU?
Regards,
Renan