This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello,
we are designing an inverter based on TMS320F28388D DSP.
Now the question about power sequencing needs to be solved. Everything is clear to us, up to this point.
During the power-up sequence, I will have VDDIO, VDD, VDDA powered correctly according the instructions in datasheet, but reference for ADC (VREFHI) can come after the input signal (AIN).
Is this a problem?
I'm expecting, that it should be not a big deal, and I will receive some mismatch data from ADC till the correct reference will be present.
BR,
Milan.
Hi Milan,
As long as the supply rails VDDIO/VDDA/VDD are powered up prior to VREFHI, it should not cause an issue even if AIN signal is present before VREFHI powers up.
Regards,
Joseph