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Hello,
I see the below information in the TRM for CLA Fixed priority arbitration scheme on Local shared Memory.
The following is the order of fixed priority for CLA accesses:
For CLA, Program Memory and Data memory cannot reside in same LSx memory block. Then why does the Program Fetch and Data Read are shown in same priority?
Ideally Program Fetch and Data access don't conflict with each other for CLA, because they must happen on different LSx RAM blocks and each LSx RAM block have their own arbitration logic. Am I right?
Best Regards
Amulrass V
Hi Amulrass,
Apologies for the delayed response.
Your query is assigned to an expert. You will get a response soon.
Regards,
Veena
Amulrass,
You are right. A particular LS memory can only be either CLA program or data.
However, CLA debug read/writes are possible on program memory(provided for debug purposes) and those writes are prioritized over program fetch
Regards,
Praveen
Hello Praveen,
Thanks for your reply. Shouldn't this need to be corrected in TRM?
Mixing of debug Reads and debug Writes along with Program Fetch in the Fixed Priority Arbiter for CLA, creates unnecessary confusion.
Now, I have further question. For CLA, which has higher priority Data Read or Data Writes (not debug modes)?
Best Regards
Amulrass V
Amulrass,
We will get the technical documentation to add more clarity here. Thanks for the input.
On your 2nd question, the CLA data writes has higher priority compared to data reads
Regards,
Praveen