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Original question:
Hello Experts,
I have following questions on C28x busses and the CPU Fixed Priority Arbiter.
1. Do all the three CPU busses (Program Read bus, Data Read bus, Data write bus) are connected to all of the following on-chip RAMs: GSx, LSx, Dx, and Mx? If no, please specify what busses are connected to each of the RAMs.
2. Is the CPU Fixed priority arbitration scheme is applicable all of the above mentioned RAMs?
3. Is the CPU Fixed priority arbiter is individually implemented for each RAM blocks or as single arbiter for each CPU?
Best Regards
Amulrass V
