This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388D: GPIO Open drain configuration

Part Number: TMS320F28388D


Hello Experts,

I need to interface an ASIC chip to TMS320F28388D device via a Parallel bus interface. The GPIOs pins assigned for the Parallel bus needs to bi-directional, i.e. It needs to be both Input and Output pin. Note that I am not intending to change the GPIO pin direction to Input/output in the run-time.

For my use-case, I intend to use Open drain configuration with Pull-up enabled for the GPIO pins. I have the following questions.

I see the following statement in TRM in the description of GPyODR register, that Open drain mode is not supported in this device. 

CAUTION: Open Drain mode is not supported on this device. Keep this bit as 0. Open drain can be emulated by
writing 0 to GPxDAT and enabling or disabling the output buffer with GPxDIR. (Peripherals such as I2C support
Open Drain mode without issue).

However, in the Sillcon errata document SPRZ458D, It is mentioned about the Open drain mode, under the title GPIO: Open-Drain Configuration may Drive a Short High Pulse. I have confusion now, Is Open drain mode is really supported or not supported in this device? If Open drain is supported, then the momentary GPIO pin glitch is the only problem which I need to take care?

Best Regards

Amulrass V