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TMS320F280049C: PPB ISR sometimes stopped

Part Number: TMS320F280049C

Hello TI-Team,

I am using the ppb for zero crossing detection and sometimes, just sometimes, the ppb ISR is stopped from being called, in mean a total loss, not single events which are not called or called to late. The PPBEventStatus is set to 7 and the event is not triggered, seems like the device would lose an interrupt and since the event status is not cleared the ISR is not called anymore, which could be caused by other interrupts in INTERRUPT_ACK_GROUP10 blocking my pbb ISR to be called and calling  Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP10) or is it a problem when multiple events are triggered fast after eachother? The voltage soc is triggered with about 51 kHz. 

My code:

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void initZeroCrossing( void )
{
uint16_t zeroRef = getZeroRefVoltage();
// Map ISR functions
Interrupt_register(INT_ADCB_EVT, &crossingZeroISR);
// Enable specific PIE & CPU interrupts:
Interrupt_enable(INT_ADCB_EVT);
// Asscociate PPB1 with ADC_SOC_115_VOL
ADC_setupPPB(ADCB_BASE, ADC_PPB_NUMBER1, ADC_SOC_115_VOL);
// calibrtion offset to detect zero
ADC_setPPBReferenceOffset(ADCB_BASE, ADC_PPB_NUMBER1, zeroRef);
// clear register once
ADC_clearPPBEventStatus(ADCB_BASE, ADC_PPB_NUMBER1, ADC_EVT_TRIPLO
| ADC_EVT_TRIPHI | ADC_EVT_ZERO);
// Enable crossing zero to generate interrupt
ADC_enablePPBEventInterrupt(ADCB_BASE, ADC_PPB_NUMBER1, ADC_EVT_ZERO);
}
// my ISR:
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 

Now my question: 

Since missing single zero crossing events is not to bad will ADC_enablePPBEventCBCClear do the trick or is there a better way to do it? 

Is the explanation valid, that the interrupt is overflown? Can I somehow catch this state? I currently use a counter to detect if the interrupt is not triggered anymore. 

Furthermore: ADC_SOC_115_VOL is soc zero, this is not the problem in this particular case?

Thanks in advance.

  • Hi,

    Yes, interrupt overflow could be the issue. Also can you check in the ISR if other flags related to limit hi and lo are also getting set.

    Thanks
    Vasudha

  • They are set, yes, but only zero interruplt is enabled.

  • Hi,

    Yes, I think using cycle by cycle clear logic (CBCEN) would be the best way to handle the overflow. Let me know if using CBEN resolves the issue.

    Thanks
    Vasudha

  • You did not answer the question why I see trip high/ trip low interrupt flags and not only crossing zero interrupt flag. And is it possible to make crossing zero detection only tripping when tripping from low to high? Furthermore, is it possible to use e.g. ECAP or any other modules to determine the timings when the interrupt was set? 

    I would like to measure the frequency of my power system. When my interrupt gets delayed by other interrupts the accuracy drops, so measuring time in the ISR routine is not the best option. I will filter my measurements, but I want to have the best guess before filtering.