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Dear team:
When my customer was testing HRPWM, he found that the period of PWM would have a jitter of 2*TBCLK.
That is, a frequency jitter of 8Hz appears at a frequency of 20KHz, which is shown in the red part of the waveform in the figure below.
The following is his code:
uint16_t period; period = DEVICE_SYSCLK_FREQ / frq; // Enable ePWMx clock SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); // Enable HRPWM clock SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); // Disable sync(Freeze clock to PWM as well) SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); // Set AQ HRPWM_setActionQualifierAction(PSFB_X_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); HRPWM_setActionQualifierAction(PSFB_X_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); HRPWM_setActionQualifierAction(PSFB_X_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); HRPWM_setActionQualifierAction(PSFB_X_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); // Set up TBPRD EPWM_setTimeBasePeriod(PSFB_X_BASE, period - 1); EPWM_setTimeBaseCounter(PSFB_X_BASE, 0U); EPWM_setClockPrescaler(PSFB_X_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); // Set compare value EPWM_setCounterCompareValue(PSFB_X_BASE, EPWM_COUNTER_COMPARE_A, period >> 1); // Set counter mode UP EPWM_setTimeBaseCounterMode(PSFB_X_BASE, EPWM_COUNTER_MODE_UP); // Set period load mode shadowing EPWM_setPeriodLoadMode(PSFB_X_BASE, EPWM_PERIOD_SHADOW_LOAD); // Set compare value load mode shadowing EPWM_setCounterCompareShadowLoadMode(PSFB_X_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_PERIOD); // Enable auto-conversion HRPWM_enableAutoConversion(PSFB_X_BASE); // Set MEP control on both edges HRPWM_setMEPEdgeSelect(PSFB_X_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE); // Enable phase shift load EPWM_enablePhaseShiftLoad(PSFB_X_BASE); HRPWM_enablePhaseShiftLoad(PSFB_X_BASE); // Enable high-resolution period control HRPWM_enablePeriodControl(PSFB_X_BASE); // Enable sync(Freeze clock to PWM as well) SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); // Calling SFO() updates the HRMSTEP register with calibrated MEP_ScaleFactor. // HRMSTEP must be populated with a scale factor value prior to enabling // high resolution period control. while(status == SFO_INCOMPLETE) { status = SFO(); if(status == SFO_ERROR) { ESTOP0; // SFO function returns 2 if an error occurs & # of MEP } // steps/coarse step exceeds maximum of 255. } // Force a software sync pulse EPWM_forceSyncPulse(PSFB_X_BASE);
Is there a problem with the program?
Best regards
You need to SET on CMPAU and CLEAR on CMPAD. You need to center the wave around CTR=PRD event.