TMS320F28069: Sending more than 4 words with SPI Communication

Andrew Butler

Part Number: TMS320F28069

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void spi_fifo_init()
{
// Initialize SPI FIFO registers
   SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI
   SpiaRegs.SPICCR.all=0x001F;       //16-bit character, Loopback mode
   SpiaRegs.SPICTL.all=0x0017;       //Interrupt enabled, Master/Slave XMIT enabled
   SpiaRegs.SPISTS.all=0x0000;
   SpiaRegs.SPIBRR=0x0063;           // Baud rate
//   SpiaRegs.SPIFFTX.all=0xC022;      // Enable FIFO's, set TX FIFO level to 4
   SpiaRegs.SPIFFTX.all=0xC021;      // Enable FIFO's, set TX FIFO level to 1
//   SpiaRegs.SPIFFRX.all=0x0022;      // Set RX FIFO level to 4
   SpiaRegs.SPIFFRX.all=0x4021;      // Set RX FIFO level to 1
   SpiaRegs.SPIFFCT.all=0x00;
   SpiaRegs.SPIPRI.all=0x0010;
   SpiaRegs.SPICCR.bit.SPISWRESET=1;  // Enable SPI
   SpiaRegs.SPIFFTX.bit.TXFIFO=1;
   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
}
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void spi_fifo_init()
{
// Initialize SPI FIFO registers
   SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI

   SpiaRegs.SPICCR.all=0x001F;       //16-bit character, Loopback mode
   SpiaRegs.SPICTL.all=0x0017;       //Interrupt enabled, Master/Slave XMIT enabled
   SpiaRegs.SPISTS.all=0x0000;
   SpiaRegs.SPIBRR=0x0063;           // Baud rate
//   SpiaRegs.SPIFFTX.all=0xC022;      // Enable FIFO's, set TX FIFO level to 4
   SpiaRegs.SPIFFTX.all=0xC021;      // Enable FIFO's, set TX FIFO level to 1
//   SpiaRegs.SPIFFRX.all=0x0022;      // Set RX FIFO level to 4
   SpiaRegs.SPIFFRX.all=0x4021;      // Set RX FIFO level to 1
   SpiaRegs.SPIFFCT.all=0x00;
   SpiaRegs.SPIPRI.all=0x0010;

   SpiaRegs.SPICCR.bit.SPISWRESET=1;  // Enable SPI

   SpiaRegs.SPIFFTX.bit.TXFIFO=1;
   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
}

Void NVM_TX_HWI()
{
    Uint16 i;

    SpiaRegs.SPITXBUF = 0x06;               // Set write enable latch (WREN)
    SpiaRegs.SPITXBUF = 0x02;               // Write memory data (WRITE)
    SpiaRegs.SPITXBUF = 0x00;               // Memory address of write location (MSB)
    SpiaRegs.SPITXBUF = 0x00;               // Memory address of write location
//    SpiaRegs.SPITXBUF = 0x00;               // Memory address of write location (LSB)
    SpiaRegs.SPITXBUF = rdata_point++;                // Data to Write

    DELAY_US(1000000L);

    SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x20;       // Issue PIE ACK
}

Void NVM_RX_HWI()
{
    Uint16 i;

    rdata[rcount++]=SpiaRegs.SPIRXBUF;     // Read data
    if(rcount>=4) rcount=0;

    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x20;       // Issue PIE ack
}

I am trying to test the SPI code that I leveraged from the SPI loopback example. I am trying to send and receive more than 4 words but I can not figure out how to do so. I have attached my configuration ( spi_fifo_init() ) and the transmit and receive interrupts that handle the sending and receiving of the messages with BIOS Hardware Interrupts. What can I do to send and receive more than 4 words?

over 3 years ago

0 Gus Martinez over 3 years ago

TI__Mastermind 27961 points

Andrew,

The F28069 only has a 4-level FIFO. You are writing too much data in your ISR. You will have to poll the TXFFST bits to figure out how much space is left in the FIFO before writing to it.

0 Andrew Butler over 3 years ago in reply to Gus Martinez

Expert 2520 points

So if I don't use the ISR and poll the TX buffer then I can send more 4 words?

0 Gus Martinez over 3 years ago in reply to Andrew Butler

TI__Mastermind 27961 points

You can still use the ISR, you just have to poll the FIFO status before writing to make sure there is space in the FIFO before writing new data. Keep in mind that the SPI is shifting data at much lower speed than the CPU is writing.

0 Andrew Butler over 3 years ago in reply to Gus Martinez

Expert 2520 points

Does the chip select line get deactivated after each word is transmitted?

0 Gus Martinez over 3 years ago in reply to Andrew Butler

TI__Mastermind 27961 points

The chip select line will stay active as long as there is data in the FIFO.

0 Andrew Butler over 3 years ago in reply to Gus Martinez

Expert 2520 points

My code now is polling TXFFST until it is empty before it sends the next message. So that means the chip select is deactivating after each send? So I need to at least send the next message with at least 1 message still in TXFFST in order to keep the chip select active?

0 Gus Martinez over 3 years ago in reply to Andrew Butler

TI__Mastermind 27961 points

The last data has to be shifted out of the SPITXBUF before the chip select deactivates. So I believe the answer to your question really depends on whether your code writes a new value to the TXFIFO before SPITXBUF is empty. Have you probed the chip select line using a scope?

You technically don't have to wait until the FIFO is fully empty before writing to it. You just need to pause writing if TXFFST=4 (i.e. FIFO full). Below is sample code from driverlib (not supported by F28069 unfortunately).

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SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ASSERT(SPI_isBaseValid(base));
    //
    // Wait until space is available in the receive FIFO.
    //
    while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL)
    {
    }
    //
    // Write data to the transmit buffer.
    //
    HWREGH(base + SPI_O_TXBUF) = data;
}
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SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ASSERT(SPI_isBaseValid(base));

    //
    // Wait until space is available in the receive FIFO.
    //
    while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL)
    {
    }

    //
    // Write data to the transmit buffer.
    //
    HWREGH(base + SPI_O_TXBUF) = data;
}

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TMS320F28069: Sending more than 4 words with SPI Communication