Hello TI-Team,
I run into an error when using the serial flash programmer tool. So far I using the serial flash programmer tool was never a problem, the main thing which changed from build where I succeeded flashing and build where I get this particular error is the size.
The first part just seems to work well. Then I select 1, after some time the following error message occurs:
Application load successful!
Done waiting for application to download and boot...
SUCCESS of Command
ERROR Status: PROGRAM_ERROR
ERROR Address: 0x7200
When I reduce the size by raising my optimization level (which is not an option just for testing, since all test where made on lower optimization level) I am able to flash the device. The code is only on one flash bank. All sections where combined in one flash bank.
From: software-dl.ti.com/.../c2000_c28x-compiler-understanding-linking.html
- Flash sectors can be combined to form larger memory segments. The thing to keep in mind is the smallest amount that can be erased is a physical sector. This may affect how code is partitioned for field upgrades.
I also combined two
My Linker Command File:
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x0000F3, length = 0x00030D /* private ram of the cpu */
/* LSx: By default, these memories are dedicated only to the CPU, and the user could choose to share these memories */
/* with the CLA */
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* last bytes of flash bank 0 are preserved for linker genereated crc table*/
FLASH_CRC_TABLE : origin = 0x080002, length = 0x00003E /* on-chip Flash */
FLASH_BANK0 : origin = 0x080040, length = 0x00FFC0 /* on-chip Flash */
/* BANK 1 */
FLASH_BANK1 : origin = 0x090000, length = 0x00FFF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* LSx: By default, these memories are dedicated only to the CPU, and the user could choose to share these memories */
/* with the CLA */
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
/* GSx: Global shared ram accessible from both the CPU and DMA*/
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS23 : origin = 0x010000, length = 0x003FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}
SECTIONS
{
codestart : > BEGIN, PAGE = 0, ALIGN(4), crc_table(linkerCrcTable, algorithm=CRC32_PRIME)
.text : >> FLASH_BANK0,
PAGE = 0, ALIGN(4), crc_table(linkerCrcTable, algorithm=CRC32_PRIME)
.cinit : > FLASH_BANK0, PAGE = 0, ALIGN(4), crc_table(linkerCrcTable, algorithm=CRC32_PRIME)
.switch : LOAD = FLASH_BANK0, PAGE = 0 , crc_table(linkerCrcTable, algorithm=CRC32_PRIME)
RUN = RAMLS2, PAGE = 0 /* Run section from RAM */
LOAD_START(_switch_loadstart),
RUN_START(_switch_runstart),
SIZE(_switch_size)
/* Initalized sections go in Flash */
.const : >> FLASH_BANK0, PAGE = 0, ALIGN(4) , crc_table(linkerCrcTable, algorithm=CRC32_PRIME)
/* here the linker stores the CRC table */
.TI.crctab : > FLASH_CRC_TABLE, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
.stack : > RAMGS0, PAGE = 1
LOAD_START(stackStartAddress),
LOAD_SIZE(stackSize)
.bss : > RAMGS1, PAGE = 1
.bss:output : > RAMLS3, PAGE = 0
.bss:cio : > RAMLS0, PAGE = 0
.data : >> RAMLS5 | RAMLS6 | RAMLS7, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
ramgs23 : > RAMGS23, PAGE = 1
.ramm1 : > RAMM1, PAGE = 1
.TI.ramfunc : LOAD = FLASH_BANK0,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
}
