TMS320F280049: CLB COUNTER module BUG

Bruce(Shanghai) Liu

When the customer uses the CLB module for current protection, their counter module is configured as follow. The reason for setting two adjacent matches is that the customer is worried that the counter will not be detected, so it is detected and protected within two counting times.

A strange phenomenon occurred during the experiment. The action of match1 is normal, that is, when the counter value is equal to 20, it is set to 1, otherwise it is zero. However, the action of match2 is abnormal. when the counter value is equal to 21, it is set to 1,but when the counter value is other values, the counter value is still not cleared. The above situation causes match2 always be 1 after the previous fault is cleared, so the system cannot return to normal operation. It should be noted that this phenomenon cannot be reproduced every time, there may be a one-half chance. I want to confirm whether this problem may occur in the design of the counter module in our CLB when it implements the match of adjacent count values? And how to avoid it?

over 4 years ago

0 Nima Eskandari over 4 years ago

TI__Guru 52080 points

You are monitoring match1 and match2 on the oscilloscope?

0 Bruce(Shanghai) Liu over 4 years ago in reply to Nima Eskandari

TI__Intellectual 1010 points

Sure, I output match1 and match2 value through the DAC. I just want to confirm whether this problem may occur in the design of the counter module in our CLB when it implements the match of adjacent count values? And how to avoid it? Or is there any document of CLB internal design for reference？

0 Nima Eskandari over 4 years ago in reply to Bruce(Shanghai) Liu

TI__Guru 52080 points

I dont know of any such issue. Can you take out the match1 and match2 signals to GPIOs using GPIO OUTPUT XBAR?

0 Bruce(Shanghai) Liu over 4 years ago in reply to Nima Eskandari

TI__Intellectual 1010 points

Hi Nima,

The test result is as follow:

1.CLB configuration

2. I/O port configuration

XBAR_setOutputMuxConfig(XBAR_OUTPUT5,XBAR_OUT_MUX01_CLB1_OUT4);
XBAR_enableOutputMux(XBAR_OUTPUT5,XBAR_MUX01);

GPIO_setPinConfig(GPIO_7_OUTPUTXBAR5);//(GPIO_7_GPIO7); //设置为GPIO
GPIO_setDirectionMode(7, GPIO_DIR_MODE_OUT); //设置为out
GPIO_writePin(7, 0); //默认输出低电平

3. Test result(Yellow—match2, green—protection signal input from DSP, protection signal low level means match2 needs to output high level to block PWM)

(1) Normal waveform

artificially simulate abnormal conditions artificially simulate abnormal conditions (zoom in)

(2) Bug waveform

The moment of startup artificially simulate abnormal conditions

In summary, match2 has been in an abnormal state after power-on during the bug.

0 Bruce(Shanghai) Liu over 4 years ago in reply to Nima Eskandari

TI__Intellectual 1010 points

Hi Nima,

The test result is as follow:

1.CLB configuration

2. I/O port configuration

XBAR_setOutputMuxConfig(XBAR_OUTPUT5,XBAR_OUT_MUX01_CLB1_OUT4);
XBAR_enableOutputMux(XBAR_OUTPUT5,XBAR_MUX01);

GPIO_setPinConfig(GPIO_7_OUTPUTXBAR5);//(GPIO_7_GPIO7); //设置为GPIO
GPIO_setDirectionMode(7, GPIO_DIR_MODE_OUT); //设置为out
GPIO_writePin(7, 0); //默认输出低电平

3. Test result(Yellow—match2, green—protection signal input from DSP, protection signal low level means match2 needs to output high level to block PWM)

(1) Normal waveform

artificially simulate abnormal conditions artificially simulate abnormal conditions (zoom in)

(2) Bug waveform

The moment of startup artificially simulate abnormal conditions

In summary, match2 has been in an abnormal state after power-on during the bug.

0 Nima Eskandari over 4 years ago in reply to Bruce(Shanghai) Liu

TI__Guru 52080 points

So it's only abnormal once after POWER ON?

0 Bruce(Shanghai) Liu over 4 years ago in reply to Nima Eskandari

TI__Intellectual 1010 points

It looks like this, and it cannot be recovered after an abnormality occurs when the power is turned on. It may be that the initialization is not successful.

0 Bruce(Shanghai) Liu over 4 years ago in reply to Bruce(Shanghai) Liu

TI__Intellectual 1010 points

The initialization code is as follows, you can refer to The initialization code is as follows, you can refer to

void sDrv_InitClb(void)
{
EALLOW;
CpuSysRegs.PCLKCR17.bit.CLB1 = 1;
CpuSysRegs.PCLKCR17.bit.CLB2 = 1;
CpuSysRegs.PCLKCR17.bit.CLB3 = 1;
CpuSysRegs.PCLKCR17.bit.CLB4 = 1;
EDIS;
//对外部的过流信号的GPIO进行配置
// Configure GPIO12 for Button
GPIO_setPinConfig(GPIO_57_GPIO57); // 逆变过流信号
GPIO_setDirectionMode(57, GPIO_DIR_MODE_IN); // 配置为输入
GPIO_setQualificationMode(57,GPIO_QUAL_6SAMPLE);// 配置采样窗3个周期
GPIO_setPadConfig(57, GPIO_PIN_TYPE_PULLUP); // 开启输入上拉

// Configure GPIO25 for Button
GPIO_setPinConfig(GPIO_58_GPIO58); // PV过流信号
GPIO_setDirectionMode(58, GPIO_DIR_MODE_IN); // 配置为输入
GPIO_setQualificationMode(58,GPIO_QUAL_6SAMPLE);// 配置采样窗3个周期
GPIO_setPadConfig(58, GPIO_PIN_TYPE_PULLUP); // 开启输入上拉

// Configure Input-XBAR INPUT1/2 to GPIOx //将外部GPIO映射到INPUT-Xbar中
#if defined(DRV_PLAT_TYPE_F28003x)
XBAR_setInputPin(INPUTXBAR_BASE, XBAR_INPUT1, 57); //逆变过流信号--->XBAR1
XBAR_setInputPin(INPUTXBAR_BASE, XBAR_INPUT2, 58); //PV过流信号--->XBAR2
#else
XBAR_setInputPin(XBAR_INPUT1, 57); //逆变过流信号--->XBAR1
XBAR_setInputPin(XBAR_INPUT2, 58); //PV过流信号--->XBAR2
#endif

// Configure CLB-XBAR AUXSIG0/1/2 as INPUT1/2/3 //将INPUT-Xbar映射到CLB-Xbar中
XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX01_INPUTXBAR1); // 逆变硬件过流信号--->XBAR1--->AUXSIG0
XBAR_enableCLBMux(XBAR_AUXSIG0, XBAR_MUX01);
XBAR_setCLBMuxConfig(XBAR_AUXSIG1, XBAR_CLB_MUX03_INPUTXBAR2); // PV硬件过流信号--->XBAR2--->AUXSIG1
XBAR_enableCLBMux(XBAR_AUXSIG1, XBAR_MUX03);

XBAR_setCLBMuxConfig(XBAR_AUXSIG2, XBAR_CLB_MUX00_CMPSS1_CTRIPH); // PV1 cmpss过流流信号--->CMP1_H--->AUXSIG2
XBAR_enableCLBMux(XBAR_AUXSIG2, XBAR_MUX00);
XBAR_setCLBMuxConfig(XBAR_AUXSIG3, XBAR_CLB_MUX04_CMPSS3_CTRIPH); // PV2 cmpss过流流信号--->CMP3_H--->AUXSIG3
XBAR_enableCLBMux(XBAR_AUXSIG3, XBAR_MUX04);
XBAR_setCLBMuxConfig(XBAR_AUXSIG4, XBAR_CLB_MUX12_CMPSS7_CTRIPH); // INV cmpss过流流信号--->CMP7_H--->AUXSIG4
XBAR_enableCLBMux(XBAR_AUXSIG4, XBAR_MUX12);
XBAR_setCLBMuxConfig(XBAR_AUXSIG5, XBAR_CLB_MUX13_CMPSS7_CTRIPL); // INV cmpss过流流信号--->CMP7_L--->AUXSIG5
XBAR_enableCLBMux(XBAR_AUXSIG5, XBAR_MUX13);
XBAR_setCLBMuxConfig(XBAR_AUXSIG6, XBAR_CLB_MUX02_CMPSS2_CTRIPH); // bus过压信号--->CMP2_H--->AUXSIG6
XBAR_enableCLBMux(XBAR_AUXSIG6, XBAR_MUX02);
// init clb1
CLB_enableCLB(CLB1_BASE);
initTILE1(CLB1_BASE);
//configure PWM as CLB input
// Select Global input instead of local input for all CLB IN
CLB_configLocalInputMux(CLB1_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN2, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN5, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN6, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN7, CLB_LOCAL_IN_MUX_GLOBAL_IN);

// Select EPWMxA/B for CLBx, IN0/1
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM1A);
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM1B);
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN2, CLB_GLOBAL_IN_MUX_EPWM2A);
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN3, CLB_GLOBAL_IN_MUX_EPWM2B);
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN4, CLB_GLOBAL_IN_MUX_CLB_AUXSIG0); // 逆变硬件过流信号--->XBAR1--->AUXSIG0
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN5, CLB_GLOBAL_IN_MUX_CLB_AUXSIG6); // bus过压信号--->CMP2_H--->AUXSIG6
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN6, CLB_GLOBAL_IN_MUX_CLB2_OUT17); // INV cmpss过流流信号由CLB2输出
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN7, CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR);

// Select External for CLBx, IN0/1
CLB_configGPInputMux(CLB1_BASE, CLB_IN0, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN1, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN2, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN3, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN4, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN5, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN6, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN7, CLB_GP_IN_MUX_GP_REG); // 软件清除保护信号输入

// CLB1_IN0 - third mux selects a pulse version of the output from the second mux
CLB_selectInputFilter(CLB1_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN2, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN3, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN4, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN5, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN6, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN7, CLB_FILTER_NONE);

CLB_setOutputMask(CLB1_BASE, CLB_OUTPUT_00, true); // output EPWM1A
CLB_setOutputMask(CLB1_BASE, CLB_OUTPUT_02, true); // output EPWM1B
CLB_setGPREG(CLB1_BASE, 0); // 门控清零

// Clb1LogicCtrlRegs.CLB_GP_REG.bit.SW_GATING_CTRL_0 = 1; // 输出门控与门
// Clb1LogicCtrlRegs.CLB_GP_REG.bit.SW_GATING_CTRL_2 = 1; // 输出门控与门
// Clb1LogicCtrlRegs.CLB_GP_REG.bit.SW_GATING_CTRL_1 = 1; // 输出门控与门
// Clb1LogicCtrlRegs.CLB_GP_REG.bit.SW_GATING_CTRL_3 = 1; // 输出门控与门

// init clb2
CLB_enableCLB(CLB2_BASE);
initTILE2(CLB2_BASE);
//configure PWM as CLB input
// Select Global input instead of local input for all CLB IN
CLB_configLocalInputMux(CLB2_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN2, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN5, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN6, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB2_BASE, CLB_IN7, CLB_LOCAL_IN_MUX_GLOBAL_IN);

// Select EPWMxA/B for CLBx, IN0/1
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_CLB1_OUT17);
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_CLB1_OUT19);
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN2, CLB_GLOBAL_IN_MUX_CLB_AUXSIG4); // INV cmpss过流流信号--->CMP7_H--->AUXSIG4
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN3, CLB_GLOBAL_IN_MUX_CLB_AUXSIG5); // INV cmpss过流流信号--->CMP7_L--->AUXSIG5
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN4, CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR);
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN5, CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR);
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN6, CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR);
CLB_configGlobalInputMux(CLB2_BASE, CLB_IN7, CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR);

// Select External for CLBx, IN0/1
CLB_configGPInputMux(CLB2_BASE, CLB_IN0, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB2_BASE, CLB_IN1, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB2_BASE, CLB_IN2, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB2_BASE, CLB_IN3, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB2_BASE, CLB_IN4, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB2_BASE, CLB_IN5, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB2_BASE, CLB_IN6, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB2_BASE, CLB_IN7, CLB_GP_IN_MUX_GP_REG);

// CLB2_IN0 - third mux selects a pulse version of the output from the second mux
CLB_selectInputFilter(CLB2_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB2_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB2_BASE, CLB_IN2, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB2_BASE, CLB_IN3, CLB_FILTER_NONE);

CLB_setOutputMask(CLB2_BASE, CLB_OUTPUT_00, true); // output EPWM2A
CLB_setOutputMask(CLB2_BASE, CLB_OUTPUT_02, true); // output EPWM2B
CLB_setGPREG(CLB2_BASE, 0); // 门控清零

// init clb3
CLB_enableCLB(CLB3_BASE);
initTILE3(CLB3_BASE);
//configure PWM as CLB input
// Select Global input instead of local input for all CLB IN
CLB_configLocalInputMux(CLB3_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN2, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN5, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN6, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB3_BASE, CLB_IN7, CLB_LOCAL_IN_MUX_GLOBAL_IN);

// Select EPWMxA/B for CLBx, IN0/1
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM3A);
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM4A);
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN2, CLB_GLOBAL_IN_MUX_CLB_AUXSIG1); // PV硬件过流信号--->XBAR2--->AUXSIG1
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN3, CLB_GLOBAL_IN_MUX_CLB_AUXSIG2); // PV1 cmpss过流流信号--->CMP1_H--->AUXSIG2
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN4, CLB_GLOBAL_IN_MUX_CLB_AUXSIG3); // PV2 cmpss过流流信号--->CMP3_H--->AUXSIG3
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN5, CLB_GLOBAL_IN_MUX_CLB_AUXSIG6); // bus过压信号--->CMP2_H--->AUXSIG6
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN6, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB3_BASE, CLB_IN7, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);

// Select External for CLBx, IN0/1
CLB_configGPInputMux(CLB3_BASE, CLB_IN0, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB3_BASE, CLB_IN1, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB3_BASE, CLB_IN2, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB3_BASE, CLB_IN3, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB3_BASE, CLB_IN4, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB3_BASE, CLB_IN5, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB3_BASE, CLB_IN6, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB3_BASE, CLB_IN7, CLB_GP_IN_MUX_GP_REG); // 软件清除保护信号输入

// CLB3_IN0 - third mux selects a pulse version of the output from the second mux
CLB_selectInputFilter(CLB3_BASE, CLB_IN0, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB3_BASE, CLB_IN1, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB3_BASE, CLB_IN2, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB3_BASE, CLB_IN3, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB3_BASE, CLB_IN4, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB3_BASE, CLB_IN5, CLB_FILTER_NONE);
CLB_selectInputFilter(CLB3_BASE, CLB_IN7, CLB_FILTER_NONE);

CLB_setOutputMask(CLB3_BASE, CLB_OUTPUT_00, true); // output EPWM3A
CLB_setGPREG(CLB3_BASE, 0); // 门控清零
// Clb3LogicCtrlRegs.CLB_GP_REG.bit.SW_GATING_CTRL_0 = 1; // 输出门控与门

// init clb4
CLB_enableCLB(CLB4_BASE);
initTILE4(CLB4_BASE);
//configure PWM as CLB input
// Select Global input instead of local input for all CLB IN
CLB_configLocalInputMux(CLB4_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN2, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN5, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN6, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB4_BASE, CLB_IN7, CLB_LOCAL_IN_MUX_GLOBAL_IN);

// Select EPWMxA/B for CLBx, IN0/1
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_CLB3_OUT17);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN2, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN3, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN4, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN5, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN6, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);
CLB_configGlobalInputMux(CLB4_BASE, CLB_IN7, CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR);

// Select External for CLBx, IN0/1
CLB_configGPInputMux(CLB4_BASE, CLB_IN0, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB4_BASE, CLB_IN1, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB4_BASE, CLB_IN2, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB4_BASE, CLB_IN3, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB4_BASE, CLB_IN4, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB4_BASE, CLB_IN5, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB4_BASE, CLB_IN6, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB4_BASE, CLB_IN7, CLB_GP_IN_MUX_GP_REG); // 软件清除保护信号输入

// CLB4_IN0 - third mux selects a pulse version of the output from the second mux
CLB_selectInputFilter(CLB4_BASE, CLB_IN0, CLB_FILTER_NONE);

CLB_setOutputMask(CLB4_BASE, CLB_OUTPUT_00, true); // output EPWM4A
CLB_setGPREG(CLB4_BASE, 0); // 门控清零
// Clb4LogicCtrlRegs.CLB_GP_REG.bit.SW_GATING_CTRL_0 = 1; // 输出门控与门

sDrv_Clb1FaultLockClr();
sDrv_Clb2FaultLockClr();
sDrv_Clb3FaultLockClr();
sDrv_Clb4FaultLockClr();

}

/*****************************************************************************************
Function name: sDrv_Clb1FaultLockClr
Description: .
Called method:
Parameters: void
Return: void
******************************************************************************************/
void sDrv_Clb1FaultLockClr(void)
{
Clb1LogicCtrlRegs.CLB_GP_REG.bit.REG |= DRV_CLB1_FAULT_CLR_IN_SEL;
//Clb1LogicCtrlRegs.CLB_GP_REG.bit.REG |= (DRV_CLB_GP_REG_IN4|DRV_CLB_GP_REG_IN5|DRV_CLB_GP_REG_IN6);
asm(" NOP");
Clb1LogicCtrlRegs.CLB_GP_REG.bit.REG &= (~DRV_CLB1_FAULT_CLR_IN_SEL);
}

/*****************************************************************************************
Function name: sDrv_Clb2FaultLockClr
Description: .
Called method:
Parameters: void
Return: void
******************************************************************************************/
void sDrv_Clb2FaultLockClr(void)
{
Clb2LogicCtrlRegs.CLB_GP_REG.bit.REG |= DRV_CLB2_FAULT_CLR_IN_SEL;
asm(" NOP");
Clb2LogicCtrlRegs.CLB_GP_REG.bit.REG &= (~DRV_CLB2_FAULT_CLR_IN_SEL);
}

/*****************************************************************************************
Function name: sDrv_Clb3FaultLockClr
Description: .
Called method:
Parameters: void
Return: void
******************************************************************************************/
void sDrv_Clb3FaultLockClr(void)
{
Clb3LogicCtrlRegs.CLB_GP_REG.bit.REG |= DRV_CLB3_FAULT_CLR_IN_SEL;
asm(" NOP");
Clb3LogicCtrlRegs.CLB_GP_REG.bit.REG &= (~DRV_CLB3_FAULT_CLR_IN_SEL);
}

/*****************************************************************************************
Function name: sDrv_Clb4FaultLockClr
Description: .
Called method:
Parameters: void
Return: void
******************************************************************************************/
void sDrv_Clb4FaultLockClr(void)
{
Clb4LogicCtrlRegs.CLB_GP_REG.bit.REG |= DRV_CLB4_FAULT_CLR_IN_SEL;
asm(" NOP");
Clb4LogicCtrlRegs.CLB_GP_REG.bit.REG &= (~DRV_CLB4_FAULT_CLR_IN_SEL);
}

+1 Nima Eskandari over 4 years ago in reply to Bruce(Shanghai) Liu

TI__Guru 52080 points

Enable the CLB after initializing the TILE. so Call initTILE first. That should solve the issue.

0 Bruce(Shanghai) Liu over 4 years ago in reply to Nima Eskandari

TI__Intellectual 1010 points

Hi Nima,

Thanks for the support! After testing, now that the issue is solved, can you help analyze why there is such a difference? CLB is also enabled before initializing the TILE in our demo

0 Nima Eskandari over 4 years ago in reply to Bruce(Shanghai) Liu

TI__Guru 52080 points

We have been assessing the functionality of the TILE initialization while CLB is enabled. Also we have been analyzing the SYS reset on CLB TILE configurations. I will let you know when we have completed this. In general disable + Initialize first then enable. We will be updating the all of the examples.

0 Bruce(Shanghai) Liu over 4 years ago in reply to Nima Eskandari

TI__Intellectual 1010 points

That's a good news! Hope your reply soon.

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TMS320F280049: CLB COUNTER module BUG