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TMS320F28379S: CLB: count the number of PWM pulse

A GIR
Genius 3615 points
Part Number: TMS320F28379S

Hello,

I seen some CLB documentation and exemple.

Now, I try to design my own configuration.

My aim is to generate a configurable number of negative pulse.

To do this, I think use the PWM4 in input which will be configured to always generate pulse at the desired frequency.

Then, on a software signal which could imagine be an the counter mode 0 or FSM e0 set to 1 or 0 by software, when this "ENABLE" signal is set, then we wait the first PWM falling edge to copy the pwm signal to the Ouput. When the number of desired pulse is done, keep the ouput to 1 and then, wait ENABLE goes 0 and then 1 again to restart..

But my problem is how count the number of PWM pulse? The counter only allow to count with the CLBCLK, not specific input count

Thank

  • 0
    TI__Mastermind 24095 points

    Hi,

    You can simply use the edge detect on the input. Refer to "Figure 25-3. CLB Input Mux and Filter" in the device TRM.
    Refer to Table 25-50. CLB_INPUT_FILTER Register Field Descriptions
    You can set CLB_INPUT_FILTER on the corresponding input to "rising edge" detect mode.
    In this case, a single 1 CLB clock cycle pulse is generated on every rising edge of the input signal (PWM in your case).
    You can then connect this input to the counter Mode_0 input, and set Mode_1 to 1. This should count the number of pulses for you.