TMS320F28379D: Linker file memory range errors

Sinan KAMILCELEBI

Intellectual 520 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Hello,

I am using the following empty project inside C2000Ware_3_04_00_00.

C:\C2000Ware_3_04_00_00\driverlib\f2837xd\examples\dual\empty_projects

After I wrote some code in the project, I started getting the following errors.

I added the "RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3" sections to the project because of insufficient RAM.

The "2837xD_RAM_lnk_cpu1.cmd" file of my project is attached.

/cfs-file/__key/communityserver-discussions-components-files/171/2837xD_5F00_RAM_5F00_lnk_5F00_cpu1.rar

How can we solve this error?

Thanks,

Sinan.

over 3 years ago

0 Veena Kamath over 3 years ago

TI__Mastermind 32345 points

Hi Sinan,

You can combine consecutive memories to form larger emmory blocks so that tlarges sections can be fit in.

For example :

/* RAMLS4 : origin = 0x00A000, length = 0x000800 */
/* RAMLS5 : origin = 0x00A800, length = 0x000800 */
RAMLS4_5 : origin = 0x00A000, length = 0x001000

Regards,

Veena

0 Sinan KAMILCELEBI over 3 years ago in reply to Veena Kamath

Intellectual 520 points

Hi, Veena:

Veena Kamath said:
For example :

/* RAMLS4 : origin = 0x00A000, length = 0x000800 */
/* RAMLS5 : origin = 0x00A800, length = 0x000800 */
RAMLS4_5 : origin = 0x00A000, length = 0x001000

I did as you stated, but the problem is not solved.

I added RAMLS4_5 to the .text section of the linker file. Also, I set the "--gen_" settings in the image below to "on".

My "2837xD_FLASH_lnk_cpu1.cmd" file is as follows:

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MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   BEGIN            : origin = 0x000000, length = 0x000002
   RAMM0            : origin = 0x000123, length = 0x0002DD
   RAMD0            : origin = 0x00B000, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800 
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
//   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
PAGE 1 :
   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN            : origin = 0x000000, length = 0x000002
   RAMM0            : origin = 0x000123, length = 0x0002DD
   RAMD0            : origin = 0x00B000, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800 
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
//   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

//   RAMLS5      : origin = 0x00A800, length = 0x000800
   RAMLS4_5    : origin = 0x00A000, length = 0x001000

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15     : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   
//   RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
                                                            /* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
}


SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   .text            : >> RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4_5,   PAGE = 0
   .cinit           : > RAMM0,     PAGE = 0
   .switch          : > RAMM0,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   .stack           : > RAMM1,     PAGE = 1

#if defined(__TI_EABI__)
   .bss             : > RAMLS4_5,    PAGE = 1
   .bss:output      : > RAMLS3,    PAGE = 0
   .init_array      : > RAMM0,     PAGE = 0
   .const           : > RAMLS4_5,    PAGE = 1
   .data            : > RAMLS4_5,    PAGE = 1
   .sysmem          : > RAMLS4_5,    PAGE = 1
#else
   .pinit           : > RAMM0,     PAGE = 0
//   .ebss            : > RAMLS5,    PAGE = 1
   .ebss : >> RAMGS5 | RAMGS0 | RAMGS1 PAGE = 1
   .econst          : > RAMLS4_5,    PAGE = 1
   .esysmem         : > RAMLS4_5,    PAGE = 1
#endif

   Filter_RegsFile  : > RAMGS0,    PAGE = 1


   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0,      PAGE = 0
   #else
    ramfuncs    : > RAMM0      PAGE = 0   
   #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

    /* The following section definition are for SDFM examples */
   Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
   Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
   Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
   Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
   Difference_RegsFile : >RAMGS5,   PAGE = 1, fill=0x3333
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Regards,
Sinan.

0 Veena Kamath over 3 years ago in reply to Sinan KAMILCELEBI

TI__Mastermind 32345 points

Hi,

Please take a note on the error message. It says the .text is of size 0x1de7 and the individual memory blocks are of size 0x800. To fit in a section of size 0x1de7, you need to combine 4 consecutive memories

Regards,

Veena

0 Sinan KAMILCELEBI over 3 years ago in reply to Veena Kamath

Intellectual 520 points

Hi,

I combined RAMLS2, RAMLS3, RAMLS4 and RAMLS5 memory partitions. But again it didn't.

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MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   BEGIN            : origin = 0x000000, length = 0x000002
   RAMM0            : origin = 0x000123, length = 0x0002DD
   RAMD0            : origin = 0x00B000, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800 
   RAMLS1           : origin = 0x008800, length = 0x000800
//   RAMLS2           : origin = 0x009000, length = 0x000800
//   RAMLS3           : origin = 0x009800, length = 0x000800
//   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
PAGE 1 :
   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN            : origin = 0x000000, length = 0x000002
   RAMM0            : origin = 0x000123, length = 0x0002DD
   RAMD0            : origin = 0x00B000, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800 
   RAMLS1           : origin = 0x008800, length = 0x000800
//   RAMLS2           : origin = 0x009000, length = 0x000800
//   RAMLS3           : origin = 0x009800, length = 0x000800
//   RAMLS4           : origin = 0x00A000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

//   RAMLS5      : origin = 0x00A800, length = 0x000800
   RAMLS2_3_4_5    : origin = 0x009000, length = 0x002000

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15     : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   
//   RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
                                                            /* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
}


SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   .text            : >> RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2_3_4_5,   PAGE = 0
//   .text            : >> RAMD0 |  RAMLS0_1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
//   .text            : >> RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3,   PAGE = 0
   .cinit           : > RAMM0,     PAGE = 0
   .switch          : > RAMM0,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   .stack           : > RAMM1,     PAGE = 1

#if defined(__TI_EABI__)
   .bss             : > RAMLS2_3_4_5,    PAGE = 1
   .bss:output      : > RAMLS2_3_4_5,    PAGE = 0
   .init_array      : > RAMM0,     PAGE = 0
   .const           : > RAMLS2_3_4_5,    PAGE = 1
   .data            : > RAMLS2_3_4_5,    PAGE = 1
   .sysmem          : > RAMLS2_3_4_5,    PAGE = 1
#else
   .pinit           : > RAMM0,     PAGE = 0
//   .ebss            : > RAMLS5,    PAGE = 1
   .ebss : >> RAMGS5 | RAMGS0 | RAMGS1 PAGE = 1
   .econst          : > RAMLS2_3_4_5,    PAGE = 1
   .esysmem         : > RAMLS2_3_4_5,    PAGE = 1
#endif

   Filter_RegsFile  : > RAMGS0,    PAGE = 1


   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0,      PAGE = 0
   #else
    ramfuncs    : > RAMM0      PAGE = 0   
   #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

    /* The following section definition are for SDFM examples */
   Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
   Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
   Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
   Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
   Difference_RegsFile : >RAMGS5,   PAGE = 1, fill=0x3333
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Thanks,
Sinan.

0 Veena Kamath over 3 years ago in reply to Sinan KAMILCELEBI

TI__Mastermind 32345 points

Hi Sinan,

As mentioned in the error message there is no RAMLS2_3_4_5 in page 0. Please add the RAMLS2_3_4_5 definition under Page 0

Regards,

Veena

0 Sinan KAMILCELEBI over 3 years ago in reply to Veena Kamath

Intellectual 520 points

Hi, Veena:

Sinan KAMILCELEBI said:
I added the "RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3" sections to the project because of insufficient RAM.

Couldn't I have just added new RAM partition instead of combining RAM blocks?

for example:

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.text  : >> RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3,   PAGE = 0
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

.text  : >> RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3,   PAGE = 0

It didn't happen when I did it.

Thanks,
Sinan.

+1 Veena Kamath over 3 years ago in reply to Sinan KAMILCELEBI

TI__Mastermind 32345 points

Hi Sinan,

This works if the linker is able to split the .text section to smaller subsections. By default, the sections can be split at file level. If you have gen_func_subsections turned on, compiler treats each function as separate subsection. But if a single function itself is bigger than the size of a single memory block, linker cannot split this further and allocate across memory blocks. hence you need to combine memory blocks to form larger blocks.

In your case if you move the RAMLS2_3_4_5 definition under Page 0, the issue should get resolved, I believe.

In fact, it is not required to split the memories as PAGE 0 and PAGE 1. you can keep all the memory blocks in PAGE0 itself. This was required for some of the older devices to divide program and data memory. It is not mandatory for this device

Regards,

Veena

0 Sinan KAMILCELEBI over 3 years ago in reply to Veena Kamath

Intellectual 520 points

Hi, Veena:

My problem solved. I am thankful to you.

I will close this post case later.

Thank you very much for your feedbacks.

Thanks also to TI E2E for the quick support as usual.

Have a great day and keep safe at all times.

Sinan,
Thanks and best regards.

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TMS320F28379D: Linker file memory range errors