TMS320F28335: How to modify Linker CMD file "DSP2833x_Headers_nonBIOS.cmd" for flash bootlooader.

Hello, 

The linker cmd file you would want to modify would be F28335.cmd, not the file you mentioned above. The location is C2000Ware_xx\device_support\f2833x\common\cmd. 

Thanks

Anu

I remember that when I wanted to use F2833.cmd , got some build errors, so I excluded F28335.cmd and included nonBIOS variant and worked. I do not know what is the difference. Btw project setup in CCS is legacy and there is currently three cmd file STL_F28335 ( active), DSP2833x_Headers_nonBIOS.cmd(active), F28335.cmd(disable, excluded from build).

Application requires something like BIT at first so, we used safety library and its linker STL_F28335 cmd.

I have notified the expert on this subject about this thread, they will get back to you in a day. 

Anyone help ?

Ismail, 

Can you share the build errors you get when using the F28335.cmd file? This file maps sections of the program to certain sections of memory, so this is the file you need to modify. The nonBIOS file is used to map peripheral registers to memory and should not be modified. 

The bootloader project and application project should just be mapped to different sectors in their respective linker command files e.g. the bootloader can be mapped to sectors A and B and the application C and D. The linker cmd file for the bootloader should not have anything mapped to sectors C and D and the linker cmd file for the application should not have anything mapped to sectors A and B. 

Thanks

Anu

I only included F28335.cmd in the project and got these build errors.

It seems in case only F28335.cmd works, registers are not mapped, and gives linker error because of could not find safety functions.

Hi, 

DSP2833x_Headers_nonBIOS.cmd is used for Peripheral registers , hence you will need to include this (make it active). 

The errors related to PSA_CRC are probably because this sections are defined in STL_F28335. cmd file

What happens if you include all linker command files in the build?

Best Regards

Siddharth

This is the case all .cmd files are enabled. Errors seem like duplicate definitions errors due to conflicts comes from STL_F28335.cmd.

Only the case when I disabled F28335.cmd and enabled nonBIOS and STL_F28335.cmd is bulding-error free.

Hi,

Looks like you will need STL_F28335.cmd and the nonBIOS cmd file since STL_F28335 has all the memory sections defined. You don't need F28335.cmd

You can edit  STL_F28335.cmd  to map the bootloader project and application project to different sectors.

Best Regards

Siddharth

Sir, I designed a bootloader for TI ARM TMS570 series but linker file of F28335 comes to me little bit complecated.

Can u show me where I am gonna modify. Just I know is I have to assign different memory sections for both app and bootloader software and Also

assign two different reset + vector handler area.

example in above belongs to my TMS570 config

BOOTVECTORS (X) : origin=0x00000000 length=0x00000020
BOOTFLASH (RX) : origin=0x00000020 length=0x0017FFE0
APPVECTORS (RX) : origin=0x00180000 length=0x00000020
APPFLASH (RX) : origin=0x00180020 length=0x0017FFC0

I know I should do same things for F28335 also but not sure address of possible memory where I modify and size of its lenghts.

The second problem is does cause any problem to call safety applications from application instead of bootloader ?

Because in TMS570, if you enable PBIST configs in halcogen of application  instead of halcogen of bootloder 

cause failures. This makes sense because PBIST functions should execute after uC power-up, so

if there is a requirement of STL functions like this please inform me.

Hi,

It will be similar to TMS570 config but the addresses will be different.  You can take a look at the memor map mentioned in the datasheet https://www.ti.com/lit/ds/symlink/tms320f28335.pdf and ensure that different memory sections for both app and bootloader . 

Am not aware of the safety applications that you are calling from the application , hence cannot provide any suggestions .

Best Regards

Siddharth

Hi Siddharth,

STL_F28335.cmd is really complicated. 

What if I say that I want to insert my bootloader into for example flashA and app flash B. Can you show me where

I have to modify ? Actually there will be two variant of this file one of for bootlader and second one for application.

/*
//###########################################################################
//
// FILE:	F28335.cmd
//
// TITLE:	Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//   
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28335  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

    Notes: 
          Memory blocks on F28335 are uniform (ie same
          physical memory) in both PAGE 0 and PAGE 1.  
          That is the same memory region should not be
          defined for both PAGE 0 and PAGE 1.
          Doing so will result in corruption of program 
          and/or data. 
          
          L0/L1/L2 and L3 memory blocks are mirrored - that is
          they can be accessed in high memory or low memory.
          For simplicity only one instance is used in this
          linker file. 
          
          Contiguous SARAM memory blocks can be combined 
          if required to create a larger memory block. 
 */


MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2_1     : origin = 0x00A000, length = 0x000AA8     /* on-chip RAM block L2 */
   PC_TEST_1   : origin = 0x00AAA8, length = 0x000004     /* PC test function 1 */
   RAML2_2     : origin = 0x00AAAC, length = 0x000554     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF_1    : origin = 0x310000, length = 0x005554     /* on-chip FLASH */
   PC_TEST_2   : origin = 0x315554, length = 0x000004     /* PC test function 2 */
   FLASHF_2    : origin = 0x315558, length = 0x002AA8     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */   
   FLASHC_1    : origin = 0x328000, length = 0x002AA8     /* on-chip FLASH */
   PC_TEST_3   : origin = 0x32AAA8, length = 0x000004     /* PC test function 3 */
   FLASHC_2    : origin = 0x32AAAC, length = 0x005554     /* on-chip FLASH */   
   FLASHA      : origin = 0x338000, length = 0x007E80     /* on-chip FLASH */
   
   CRC_TABLE   : origin = 0x33FE80, length = 0x000100     /* Table to hold 32 golden CRC values */
   
   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
   
   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHC_1,      PAGE = 0
   .pinit              : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,    PAGE = 0
   .text               : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,       PAGE = 0
   codestart           : > BEGIN       PAGE = 0


   Flash28_API:
   {
        -l Flash28335_API_V210.lib(.econst)
        -l Flash28335_API_V210.lib(.text)
   }
   						LOAD = FLASHD,
                       	RUN = RAML0,
                       	LOAD_START(_Flash28_API_LoadStart),
                       	LOAD_END(_Flash28_API_LoadEnd),
                       	RUN_START(_Flash28_API_RunStart),
                       	PAGE = 0

   ramfuncs            : LOAD = FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0


    psa_crc             : LOAD =  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = RAML0,
                         LOAD_START(_PSA_CRCLoadStart),
                         LOAD_END(_PSA_CRCLoadEnd),
                         RUN_START(_PSA_CRCRunStart),
                         RUN_END(_PSA_CRCRunEnd),
						 LOAD_SIZE(_PSA_CRCLoadSize),
						 PAGE = 0
                         
   pc_test_section_1   : LOAD =  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = PC_TEST_1,
                         LOAD_START(_PC_Test1LoadStart),
                         LOAD_END(_PC_Test1LoadEnd),
                         RUN_START(_PC_Test1RunStart),
                         RUN_END(_PC_Test1RunEnd),
						 LOAD_SIZE(_PC_Test1LoadSize),
						 PAGE = 0





   pc_test_section_2   : > PC_TEST_2, PAGE = 0
   pc_test_section_3   : > PC_TEST_3, PAGE = 0

   STL_Test_utility  : > RAMM1, PAGE = 1
   STL_psa_crc_vars  : > RAMM1, PAGE = 1
   STL_crc_test_data : > FLASHB, PAGE = 1
   
   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   STL_CRC_calc   : > FLASHA, PAGE = 0
   STL_CRC_TABLE  : > CRC_TABLE, PAGE = 0


   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML4       PAGE = 1
   .esysmem            : > RAMM1       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,      PAGE = 0
   .switch             : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : >>  FLASHG | FLASHF_1 | FLASHF_2 |  FLASHC_1 | FLASHC_2,      PAGE = 0                  /* Math Code */
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
   
   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the 
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
   {
   
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   
   }
   */
   
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
         
   /* Allocate DMA-accessible RAM sections: */
   DMARAML4         : > RAML4,     PAGE = 1
   DMARAML5         : > RAML5,     PAGE = 1
   DMARAML6         : > RAML6,     PAGE = 1
   DMARAML7         : > RAML7,     PAGE = 1
   
   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   ZONE7DATA        : > ZONE7B,    PAGE = 1

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
   
   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Hi,

You will have two linker cmd  - one of for bootlader and second one for application. You can assign the ".text" sections to different Flash memory sections. 

Pls refer the following post 

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/384840/bootloader-c2000-linker-problem

Best Regards

Siddharth

Hi,

After reviewed old threads, made a linker and defined two variants as below.

I will copy-paste same linker and enable variant which I want to use.

I my case I want to use FLASHA  & FLASHB for bootloader and rest of flash are will be allocated for application (by starting from FLASH H).

So now, I share three linker files here first one is original one that is pulled from ti file directory in :C path of TI.

Second one is modified one for my desired bootloader setup and third one for app.

1. I will be pretty happy if you can compare these two files and tell me if you see anything is wrong.

Original Linker File:

/*
//###########################################################################
//
// FILE:	F28335.cmd
//
// TITLE:	Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//   
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28335  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

    Notes: 
          Memory blocks on F28335 are uniform (ie same
          physical memory) in both PAGE 0 and PAGE 1.  
          That is the same memory region should not be
          defined for both PAGE 0 and PAGE 1.
          Doing so will result in corruption of program 
          and/or data. 
          
          L0/L1/L2 and L3 memory blocks are mirrored - that is
          they can be accessed in high memory or low memory.
          For simplicity only one instance is used in this
          linker file. 
          
          Contiguous SARAM memory blocks can be combined 
          if required to create a larger memory block. 
 */


MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2_1     : origin = 0x00A000, length = 0x000AA8     /* on-chip RAM block L2 */
   PC_TEST_1   : origin = 0x00AAA8, length = 0x000004     /* PC test function 1 */
   RAML2_2     : origin = 0x00AAAC, length = 0x000554     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF_1    : origin = 0x310000, length = 0x005554     /* on-chip FLASH */
   PC_TEST_2   : origin = 0x315554, length = 0x000004     /* PC test function 2 */
   FLASHF_2    : origin = 0x315558, length = 0x002AA8     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */   
   FLASHC_1    : origin = 0x328000, length = 0x002AA8     /* on-chip FLASH */
   PC_TEST_3   : origin = 0x32AAA8, length = 0x000004     /* PC test function 3 */
   FLASHC_2    : origin = 0x32AAAC, length = 0x005554     /* on-chip FLASH */   
   FLASHA      : origin = 0x338000, length = 0x007E80     /* on-chip FLASH */
   
   CRC_TABLE   : origin = 0x33FE80, length = 0x000100     /* Table to hold 32 golden CRC values */
   
   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
   
   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHC_1,      PAGE = 0
   .pinit              : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,    PAGE = 0
   .text               : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,       PAGE = 0
   codestart           : > BEGIN       PAGE = 0


   Flash28_API:
   {
        -l Flash28335_API_V210.lib(.econst)
        -l Flash28335_API_V210.lib(.text)
   }
   						LOAD = FLASHD,
                       	RUN = RAML0,
                       	LOAD_START(_Flash28_API_LoadStart),
                       	LOAD_END(_Flash28_API_LoadEnd),
                       	RUN_START(_Flash28_API_RunStart),
                       	PAGE = 0

   ramfuncs            : LOAD = FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0


    psa_crc             : LOAD =  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = RAML0,
                         LOAD_START(_PSA_CRCLoadStart),
                         LOAD_END(_PSA_CRCLoadEnd),
                         RUN_START(_PSA_CRCRunStart),
                         RUN_END(_PSA_CRCRunEnd),
						 LOAD_SIZE(_PSA_CRCLoadSize),
						 PAGE = 0
                         
   pc_test_section_1   : LOAD =  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = PC_TEST_1,
                         LOAD_START(_PC_Test1LoadStart),
                         LOAD_END(_PC_Test1LoadEnd),
                         RUN_START(_PC_Test1RunStart),
                         RUN_END(_PC_Test1RunEnd),
						 LOAD_SIZE(_PC_Test1LoadSize),
						 PAGE = 0





   pc_test_section_2   : > PC_TEST_2, PAGE = 0
   pc_test_section_3   : > PC_TEST_3, PAGE = 0

   STL_Test_utility  : > RAMM1, PAGE = 1
   STL_psa_crc_vars  : > RAMM1, PAGE = 1
   STL_crc_test_data : > FLASHB, PAGE = 1
   
   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   STL_CRC_calc   : > FLASHA, PAGE = 0
   STL_CRC_TABLE  : > CRC_TABLE, PAGE = 0


   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML4       PAGE = 1
   .esysmem            : > RAMM1       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,      PAGE = 0
   .switch             : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : >>  FLASHG | FLASHF_1 | FLASHF_2 |  FLASHC_1 | FLASHC_2,      PAGE = 0                  /* Math Code */
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
   
   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the 
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
   {
   
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   
   }
   */
   
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
         
   /* Allocate DMA-accessible RAM sections: */
   DMARAML4         : > RAML4,     PAGE = 1
   DMARAML5         : > RAML5,     PAGE = 1
   DMARAML6         : > RAML6,     PAGE = 1
   DMARAML7         : > RAML7,     PAGE = 1
   
   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   ZONE7DATA        : > ZONE7B,    PAGE = 1

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
   
   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Modified Linker File for Bootloader:

/*
//###########################################################################
//
// FILE:	F28335.cmd
//
// TITLE:	Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//   
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28335  
   PAGE 0 will be used to organize program sections
   PAGE 0 will be used to organize data sections

    Notes: 
          Memory blocks on F28335 are uniform (ie same
          physical memory) in both PAGE 0 and PAGE 0.
          That is the same memory region should not be
          defined for both PAGE 0 and PAGE 0.
          Doing so will result in corruption of program 
          and/or data. 
          
          L0/L1/L2 and L3 memory blocks are mirrored - that is
          they can be accessed in high memory or low memory.
          For simplicity only one instance is used in this
          linker file. 
          
          Contiguous SARAM memory blocks can be combined 
          if required to create a larger memory block. 
 */
#define LNK_BOOTLOADER_VARIANT	(1U)
#define LNK_APPLICATION_VARIANT (0U)

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2_1     : origin = 0x00A000, length = 0x000AA8     /* on-chip RAM block L2 */
   PC_TEST_1   : origin = 0x00AAA8, length = 0x000004     /* PC test function 1 */
   RAML2_2     : origin = 0x00AAAC, length = 0x000554     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF_1    : origin = 0x310000, length = 0x005554     /* on-chip FLASH */
   PC_TEST_2   : origin = 0x315554, length = 0x000004     /* PC test function 2 */
   FLASHF_2    : origin = 0x315558, length = 0x002AA8     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */   
   FLASHC_1    : origin = 0x328000, length = 0x002AA8     /* on-chip FLASH */
   PC_TEST_3   : origin = 0x32AAA8, length = 0x000004     /* PC test function 3 */
   FLASHC_2    : origin = 0x32AAAC, length = 0x005554     /* on-chip FLASH */   
   FLASHA      : origin = 0x338000, length = 0x007E80     /* on-chip FLASH */
   CRC_TABLE   : origin = 0x33FE80, length = 0x000100     /* Table to hold 32 golden CRC values */
   
   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
   
   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : {} > FLASHA | FLASHB ,      PAGE = 0//NOLOAD SECTION, used to initailize c Global varalbles at startup, initialized section

   .pinit              : {} > FLASHA | FLASHB ,     PAGE = 0//global constructors for c++program.

   .text               : {} > FLASHA | FLASHB ,      PAGE = 0//Program code, initialized section

   codestart           : > BEGIN       PAGE = 0

   Flash28_API:
   {
        -l Flash28335_API_V210.lib(.econst)
        -l Flash28335_API_V210.lib(.text)
   }
						LOAD = FLASHA,
                       	RUN = RAML0,
                       	LOAD_START(_Flash28_API_LoadStart),
                       	LOAD_END(_Flash28_API_LoadEnd),
                       	RUN_START(_Flash28_API_RunStart),
                       	PAGE = 0
  ramfuncs             : LOAD  = FLASHA,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0

	psa_crc             : LOAD =  FLASHA,
                         RUN = RAML0,
                         LOAD_START(_PSA_CRCLoadStart),
                         LOAD_END(_PSA_CRCLoadEnd),
                         RUN_START(_PSA_CRCRunStart),
                         RUN_END(_PSA_CRCRunEnd),
						 LOAD_SIZE(_PSA_CRCLoadSize),
						 PAGE = 0
	pc_test_section_1   : LOAD =  FLASHA,
                         RUN = PC_TEST_1,
                         LOAD_START(_PC_Test1LoadStart),
                         LOAD_END(_PC_Test1LoadEnd),
                         RUN_START(_PC_Test1RunStart),
                         RUN_END(_PC_Test1RunEnd),
						 LOAD_SIZE(_PC_Test1LoadSize),
						 PAGE = 0
   pc_test_section_2   : > PC_TEST_2, PAGE = 0
   pc_test_section_3   : > PC_TEST_3, PAGE = 0

   STL_Test_utility  : > RAMM1, PAGE = 0
   STL_psa_crc_vars  : > RAMM1, PAGE = 0
   STL_crc_test_data : >> FLASHA | FLASHB , PAGE = 0/*Not Sure*/
   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0
   STL_CRC_calc   : >> FLASHA | FLASHB , PAGE = 0
   STL_CRC_TABLE  : > CRC_TABLE, PAGE = 0
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 0
   .ebss               : > RAML4       PAGE = 0
   .esysmem            : > RAMM1       PAGE = 0

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : {} > FLASHA | FLASHB ,      PAGE = 0
   .switch             : {} > FLASHA | FLASHB ,      PAGE = 0
   /* Allocate IQ math areas: */
   IQmath              : {} > FLASHA | FLASHB ,      PAGE = 0                  /* Math Code */
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD
   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the 
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
   {
   
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   
   }
   */
   
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
         
   /* Allocate DMA-accessible RAM sections: */
   DMARAML4         : > RAML4,     PAGE = 0
   DMARAML5         : > RAML5,     PAGE = 0
   DMARAML6         : > RAML6,     PAGE = 0
   DMARAML7         : > RAML7,     PAGE = 0
   
   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   ZONE7DATA        : > ZONE7B,    PAGE = 0

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Modified Linker File for Application:

/*
//###########################################################################
//
// FILE:	F28335.cmd
//
// TITLE:	Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//   
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28335  
   PAGE 0 will be used to organize program sections
   PAGE 0 will be used to organize data sections

    Notes: 
          Memory blocks on F28335 are uniform (ie same
          physical memory) in both PAGE 0 and PAGE 0.
          That is the same memory region should not be
          defined for both PAGE 0 and PAGE 0.
          Doing so will result in corruption of program 
          and/or data. 
          
          L0/L1/L2 and L3 memory blocks are mirrored - that is
          they can be accessed in high memory or low memory.
          For simplicity only one instance is used in this
          linker file. 
          
          Contiguous SARAM memory blocks can be combined 
          if required to create a larger memory block. 
 */


MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2_1     : origin = 0x00A000, length = 0x000AA8     /* on-chip RAM block L2 */
   PC_TEST_1   : origin = 0x00AAA8, length = 0x000004     /* PC test function 1 */
   RAML2_2     : origin = 0x00AAAC, length = 0x000554     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
   FLASHH      : origin = 0x300002, length = 0x007FFE     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF_1    : origin = 0x310000, length = 0x005554     /* on-chip FLASH */
   PC_TEST_2   : origin = 0x315554, length = 0x000004     /* PC test function 2 */
   FLASHF_2    : origin = 0x315558, length = 0x002AA8     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */   
   FLASHC_1    : origin = 0x328000, length = 0x002AA8     /* on-chip FLASH */
   PC_TEST_3   : origin = 0x32AAA8, length = 0x000004     /* PC test function 3 */
   FLASHC_2    : origin = 0x32AAAC, length = 0x005554     /* on-chip FLASH */   
   FLASHA      : origin = 0x338000, length = 0x007E80     /* on-chip FLASH */

   CRC_TABLE   : origin = 0x33FE80, length = 0x000100     /* Table to hold 32 golden CRC values */
   
   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x300000, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
   
   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */

}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHH  ,      PAGE = 0
   .pinit              : >   FLASHH  ,    PAGE = 0
   .text               : >  FLASHH  ,       PAGE = 0
   codestart           : > BEGIN       PAGE = 0


   Flash28_API:
   {
        -l Flash28335_API_V210.lib(.econst)
        -l Flash28335_API_V210.lib(.text)
   }
   						LOAD = FLASHH,
                       	RUN = RAML0,
                       	LOAD_START(_Flash28_API_LoadStart),
                       	LOAD_END(_Flash28_API_LoadEnd),
                       	RUN_START(_Flash28_API_RunStart),
                       	PAGE = 0

   ramfuncs            : LOAD = FLASHH  ,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0


    psa_crc             : LOAD =  FLASHH  ,
                         RUN = RAML0,
                         LOAD_START(_PSA_CRCLoadStart),
                         LOAD_END(_PSA_CRCLoadEnd),
                         RUN_START(_PSA_CRCRunStart),
                         RUN_END(_PSA_CRCRunEnd),
						 LOAD_SIZE(_PSA_CRCLoadSize),
						 PAGE = 0

   pc_test_section_1   : LOAD =  FLASHH  ,
                         RUN = PC_TEST_1,
                         LOAD_START(_PC_Test1LoadStart),
                         LOAD_END(_PC_Test1LoadEnd),
                         RUN_START(_PC_Test1RunStart),
                         RUN_END(_PC_Test1RunEnd),
						 LOAD_SIZE(_PC_Test1LoadSize),
						 PAGE = 0





   pc_test_section_2   : > PC_TEST_2, PAGE = 0
   pc_test_section_3   : > PC_TEST_3, PAGE = 0

   STL_Test_utility  : > RAMM1, PAGE = 0
   STL_psa_crc_vars  : > RAMM1, PAGE = 0
   STL_crc_test_data : > FLASHH  , PAGE = 0

   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   STL_CRC_calc   : > FLASHH, PAGE = 0
   STL_CRC_TABLE  : > CRC_TABLE, PAGE = 0



   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 0
   .ebss               : > RAML4       PAGE = 0
   .esysmem            : > RAMM1       PAGE = 0

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : >  FLASHH  ,      PAGE = 0
   .switch             : >  FLASHH  ,      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : >  FLASHH,      PAGE = 0                  /* Math Code */
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD

   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the 
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
   {
   
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   
   }
   */
   
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
         
   /* Allocate DMA-accessible RAM sections: */
   DMARAML4         : > RAML4,     PAGE = 0
   DMARAML5         : > RAML5,     PAGE = 0
   DMARAML6         : > RAML6,     PAGE = 0
   DMARAML7         : > RAML7,     PAGE = 0
   
   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   ZONE7DATA        : > ZONE7B,    PAGE = 0

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

2.I got confused about .reset and vector and BEGIN areas.

   In my opinion, both app and bootloader should have .reset and vector but for app

  their addresses should start from start address of sector which allocated for app right ?

Lastly should I modify codestart section for app ?

codestart           : > BEGIN       PAGE = 0

    RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
    VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
    .reset              : > RESET,      PAGE = 0, TYPE = DSECT
    vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

3. According to project requirements, customer wants Build in Test at startupt to check RAM, ROM, peripherals etc. 

I was doing this in startup of applications code, there was no problem. But now, bootloader codes will run, before the application.

In this case do I have to execute my bit test while program execures startup of bootloader code or at anywhere I can do this ?

Here is the core function which I performed BIT.

void STL_testDevice(void)
{
   // int8_t *reportMsg;
    uint16_t status;
        switch(gTestType)
        {
            case WAIT_FOR_TEST_CMD:

                 // wait in this state
            break;

            case TEST_CPU_REGISTERS:

                 status = 0;
                 bitRegHighErr_st.regHighBit.testCpuRegister = 0;

                 DINT;
                 status = STL_CPU_TEST_testCpuRegisters();
                 EINT;

                 if(status != SIG_CPU_REG_TEST)
                 {
                	 bitRegHighErr_st.regHighBit.testCpuRegister = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_FPU_REGISTERS:
                 status = 0;
                 bitRegHighErr_st.regHighBit.testFpuRegister = 0;

                 DINT;
                 status = STL_CPU_TEST_testFpuRegisters();
                 EINT;

                 if(status != SIG_FPU_REG_TEST)
                 {
					bitRegHighErr_st.regHighBit.testFpuRegister = 1;
					STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_SAFE_RAM_BOOTRSVD:
                 status = 0;
                 bitRegHighErr_st.regHighBit.testSafeRamBootRSVD = 0;

                 DINT;
                 status  = STL_MARCH_TEST_testSafeRam((uint32_t *)0xC000,RAM_TYPE_BOOT_RSVD);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegHighErr_st.regHighBit.testSafeRamBootRSVD = 1;
                	 STL_FAIL_SAFE_failSafe();
                 }

                  gTestType = WAIT_FOR_TEST_CMD;
             break;

             case TEST_SAFE_RAM_STACK:
                  status = 0;
                  bitRegHighErr_st.regHighBit.testSafeRamStack = 0;

                  DINT;
                  status = STL_MARCH_TEST_testSafeRam((uint32_t *)0xC000,RAM_TYPE_STACK);
                  EINT;

                  if(status != SIG_RAM_MARCH_TEST)
                  {
                	  bitRegHighErr_st.regHighBit.testSafeRamStack = 1;
                      STL_FAIL_SAFE_failSafe();
                  }

                  gTestType = WAIT_FOR_TEST_CMD;
             break;

             case TEST_SAFE_RAM_PSA_CRC:

            	 status = 0;
                  bitRegHighErr_st.regHighBit.testSafeRamPSA = 0;

                  DINT;
                  status = STL_MARCH_TEST_testSafeRam((uint32_t *)0xC000,RAM_TYPE_PSA_CRC);
                  EINT;

                  if(status != SIG_RAM_MARCH_TEST)
                  {
                	  bitRegHighErr_st.regHighBit.testSafeRamPSA = 1;
                	  STL_FAIL_SAFE_failSafe();
                  }

                  gTestType = WAIT_FOR_TEST_CMD;
             break;

             case TEST_SAFE_RAM_PIEVECTOR:


                  status = 0;
                  bitRegHighErr_st.regHighBit.testSafeRamPIEVECTOR = 0;

                  DINT;
                  status = STL_MARCH_TEST_testSafeRam((uint32_t *)0xC000,RAM_TYPE_PIE_VECTOR);
                  EINT;

                  if(status != SIG_RAM_MARCH_TEST)
                  {
                	  bitRegHighErr_st.regHighBit.testSafeRamPIEVECTOR = 1;
                      STL_FAIL_SAFE_failSafe();
                  }


                  gTestType = WAIT_FOR_TEST_CMD;

             break;

             case TEST_INTERRUPT:
                   status = 0;
                   bitRegHighErr_st.regHighBit.testInterrupt = 0;

                   DINT;
                   status = STL_INTERRUPT_TEST_testInterrupt((uint32_t *)0x8800,1);
                   STL_TEST_REPORT_clearPieRegisters();
                   EINT;

                   if(status != SIG_INTERRUPT_TEST)
                   {
                	   bitRegHighErr_st.regHighBit.testInterrupt = 1;
                      STL_FAIL_SAFE_failSafe();
                   }

                   gTestType = WAIT_FOR_TEST_CMD;
              break;

             case TEST_SAFE_RAM_PC_TEST_1:

                  status = 0;
                  bitRegHighErr_st.regHighBit.testSafeRamPC1 = 0;

                  DINT;
                  status = STL_MARCH_TEST_testSafeRam((uint32_t *)0xC000,RAM_TYPE_PC_TEST_1);
                  EINT;

                  if(status != SIG_RAM_MARCH_TEST)
                  {
                	  bitRegHighErr_st.regHighBit.testSafeRamPC1 = 1;
                      STL_FAIL_SAFE_failSafe();
                  }


                  gTestType = WAIT_FOR_TEST_CMD;
             break;

             case TEST_RAM_L0:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL0 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L0_RAM_START,(uint32_t *)L0_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL0 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

             case TEST_RAM_L1:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL1 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L1_RAM_START,(uint32_t *)L1_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL1 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;

             break;

             case TEST_RAM_L2:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL2 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L2_RAM_START,(uint32_t *)L2_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL2 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;

            break;

            case TEST_RAM_L3:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL3 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L3_RAM_START,(uint32_t *)L3_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL3 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_RAM_L4:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL4 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L4_RAM_START,(uint32_t *)L4_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL4 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_RAM_L5:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL5 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L5_RAM_START,(uint32_t *)L5_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL5 = 1;
                	 STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_RAM_L6:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL6 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L6_RAM_START,(uint32_t *)L6_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL6 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_RAM_L7:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testRamL7 = 0;

                 DINT;
                 status = STL_MARCH_TEST_testRam((uint32_t *)L7_RAM_START,(uint32_t *)L7_RAM_END);
                 EINT;

                 if(status != SIG_RAM_MARCH_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testRamL7 = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
            break;

             case TEST_FLASH_SECTOR_H:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorH = 0;
                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_H_START,(uint32_t *)FLASH_SECTOR_H_END,(uint64_t *)&gGoldenCRC[14],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testSectorH = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

            case TEST_FLASH_SECTOR_G:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorG = 0;

                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_G_START,(uint32_t *)FLASH_SECTOR_G_END,(uint64_t *)&gGoldenCRC[13],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
                	bitRegLowErr_st.regLowbit.testSectorG = 1;
                    STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

            case TEST_FLASH_SECTOR_F:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorF = 0;

                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_F_START,(uint32_t *)FLASH_SECTOR_F_END,(uint64_t *)&gGoldenCRC[12],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
					bitRegLowErr_st.regLowbit.testSectorF = 1;
					STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

            case TEST_FLASH_SECTOR_E:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorE = 0;

                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_E_START,(uint32_t *)FLASH_SECTOR_E_END,(uint64_t *)&gGoldenCRC[11],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testSectorE = 1;
                    STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

            case TEST_FLASH_SECTOR_D:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorD = 0;

                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_D_START,(uint32_t *)FLASH_SECTOR_D_END,(uint64_t *)&gGoldenCRC[10],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testSectorD = 1;
                     STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

            case TEST_FLASH_SECTOR_C:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorC = 0;

                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_C_START,(uint32_t *)FLASH_SECTOR_C_END,(uint64_t *)&gGoldenCRC[9],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testSectorC = 1;
                    STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;

            case TEST_FLASH_SECTOR_B:
                 status = 0;
                 bitRegLowErr_st.regLowbit.testSectorB = 0;

                 DINT;
                 STL_TEST_REPORT_disableFlashPreFetch();
                 status = STL_CRC_TEST_testNvMemory((uint32_t *)FLASH_SECTOR_B_START,(uint32_t *)FLASH_SECTOR_B_END,(uint64_t *)&gGoldenCRC[8],NV_TYPE_FLASH);
                 STL_TEST_REPORT_enableFlashPreFetch();
                 EINT;

                 if(status != SIG_NV_MEM_CRC_TEST)
                 {
                	 bitRegLowErr_st.regLowbit.testSectorB = 1;
                    STL_FAIL_SAFE_failSafe();
                 }

                 gTestType = WAIT_FOR_TEST_CMD;
             break;



            case TEST_NV_MEMORY_USER_OTP:
            	 status = 0;
            	 bitRegHighErr_st.regHighBit.testNvMemoryOTP = 0;

            	 DINT;
            	 STL_TEST_REPORT_disableFlashPreFetch();
    			 status = STL_CRC_TEST_testNvMemory((uint32_t *)USER_OTP_START,(uint32_t *)USER_OTP_END,(uint64_t *)&gGoldenCRC[16],NV_TYPE_USER_OTP);
            	 STL_TEST_REPORT_enableFlashPreFetch();
            	 EINT;
            	 if(status != SIG_NV_MEM_CRC_TEST)
            	 {
            		 bitRegHighErr_st.regHighBit.testNvMemoryOTP = 1;
            		 STL_FAIL_SAFE_failSafe();
            	 }

            	 gTestType = WAIT_FOR_TEST_CMD;
            break;

            case TEST_NV_MEMORY_BOOTROM:
			 	 status = 0;
			 	 bitRegHighErr_st.regHighBit.testNvMemoryBootRom = 0;

			 	 DINT;
				 STL_TEST_REPORT_disableFlashPreFetch();
			 	 status = STL_CRC_TEST_testNvMemory((uint32_t *)BOOTROM_START,(uint32_t *)BOOTROM_END,(uint64_t *)&gGoldenCRC[17],NV_TYPE_BOOTROM);
			 	 STL_TEST_REPORT_enableFlashPreFetch();
				 EINT;

			 	 if(status != SIG_NV_MEM_CRC_TEST)
			 	 {
			 		bitRegHighErr_st.regHighBit.testNvMemoryBootRom = 1;
			 		STL_FAIL_SAFE_failSafe();
				 }

			 	 gTestType = WAIT_FOR_TEST_CMD;
		    break;

            case TEST_PROGRAM_COUNTER:
				 status = 0;
				 bitRegHighErr_st.regHighBit.testProgramCount = 0;

				 DINT;
			     status = STL_PC_TEST_testPcRegister();
			     EINT;
				 if(status != SIG_PC_TEST)
				 {
					bitRegHighErr_st.regHighBit.testProgramCount = 1;
					STL_FAIL_SAFE_failSafe();
				 }

			 	 gTestType = WAIT_FOR_TEST_CMD;
			break;


            case TEST_TIMER_2: // start up test only

				IER &= 0x8000;// disable all interrupts except SPC detect (RTOS isr) = 0;
				status = 0;
				testTimerObject.testScaler = 9;
				testTimerObject.testPeriodCount = 14;
				testTimerObject.delayCount = 7240;
				testTimerObject.testTimer = 0;
				pTestTimer = (STL_TIMER_TEST_timerTest_Handle)&testTimerObject;
				perErrorCode_st.perErrorBit.testTimer2 = 0;
				DINT;
				status = STL_TIMER_TEST_testTimer(pTestTimer);
				STL_TEST_REPORT_TIMER_configTimer(1);
				STL_TEST_REPORT_TIMER_startTimer();
				EINT;

				if (status != SIG_TIMER_TEST)
				{
					perErrorCode_st.perErrorBit.testTimer2 = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;
			break;

			case TEST_TIMERS_0_1:
				// Test timer 1
				IER &= 0x8000; // disable all interrupts except SPC detect (RTOS isr) = 0;
				status = 0;
				testTimerObject.testScaler = 9;
				testTimerObject.testPeriodCount = 14;
				testTimerObject.delayCount = 7240;
				testTimerObject.testTimer = 0;

				pTestTimer = (STL_TIMER_TEST_timerTest_Handle) &testTimerObject;

				perErrorCode_st.perErrorBit.testTimer01 = 0;
				DINT;

				status = STL_TIMER_TEST_testTimer(pTestTimer);

				EINT;

				if (status != SIG_TIMER_TEST)
				{
					perErrorCode_st.perErrorBit.testTimer01 = 1;
					STL_FAIL_SAFE_failSafe();
				}

				IER |= M_INT14; // enable timer ISR
				// Test timer 2
				IER &= 0x8000; // disable all interrupts except SPC detect (RTOS isr) = 0;
				status = 0;
				testTimerObject.testTimer = 1;
				perErrorCode_st.perErrorBit.testTimer2 = 0;
				DINT;
				status = STL_TIMER_TEST_testTimer(pTestTimer);
				EINT;
				if (status != SIG_TIMER_TEST)
				{
					perErrorCode_st.perErrorBit.testTimer2 = 1;
					STL_FAIL_SAFE_failSafe();
				}
				IER |= M_INT14; // enable timer ISR

				gTestType = WAIT_FOR_TEST_CMD;
			break;

			case TEST_WATCHDOG: // start up test only
				IER &= 0x8000; // disable all interrupts except SPC detect (RTOS isr)
				status = 0;
				bitRegHighErr_st.regHighBit.testWatchDog = 0;
				DINT;

				status = STL_WATCHDOG_TEST_testWatchdog(47000);

				EINT;
				if (status != SIG_WDT_TEST)
				{
					bitRegHighErr_st.regHighBit.testWatchDog = 1;
					STL_FAIL_SAFE_failSafe();
				}
				gTestType = WAIT_FOR_TEST_CMD;
				IER |= M_INT14; // enable timer ISR

			break;

			case TEST_GPIO_INPUT:

				// GPIO 59 has a low volt input
				status = 0;
				perErrorCode_st.perErrorBit.testGpioInput = 0;
				DINT;

				status = STL_GPIO_TEST_testGpioInput(59, 0, 30);

				EINT;
				if (status != SIG_GPIO_INPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioInput = 1;
					STL_FAIL_SAFE_failSafe();
				}

				// GPIO 63 has a high volt input
				status = 0;

				DINT;
				status = STL_GPIO_TEST_testGpioInput(63, 1, 30);
				EINT;
				if (status != SIG_GPIO_INPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioInput = 1;
					STL_FAIL_SAFE_failSafe();
				}

				// GPIO 62 has a low volt input
				status = 0;

				DINT;
				status = STL_GPIO_TEST_testGpioInput(62, 0, 30);
				EINT;
				if (status != SIG_GPIO_INPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioInput = 1;
					STL_FAIL_SAFE_failSafe();
				}

				// GPIO 9 has a high volt input
				status = 0;

				DINT;
				status = STL_GPIO_TEST_testGpioInput(9, 1, 30);
				EINT;
				if (status != SIG_GPIO_INPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioInput = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;

			break;

			case TEST_GPIO_OUTPUT:

				// GPIO 60
				status = 0;
				perErrorCode_st.perErrorBit.testGpioOut = 0;
				DINT;

				status = STL_GPIO_TEST_testGpioOutput(60, 30);

				EINT;
				if (status != SIG_GPIO_OUTPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioOut = 1;
					STL_FAIL_SAFE_failSafe();
				}

				// GPIO 61
				status = 0;
				DINT;
				status = STL_GPIO_TEST_testGpioOutput(61, 30);
				EINT;
				if (status != SIG_GPIO_OUTPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioOut = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;

				// GPIO 6
				status = 0;
				DINT;
				status = STL_GPIO_TEST_testGpioOutput(6, 30);
				EINT;
				if (status != SIG_GPIO_OUTPUT_TEST)
				{
					perErrorCode_st.perErrorBit.testGpioOut = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;

			break;

			case TEST_SPI: // start up test only

				status = 0;
				perErrorCode_st.perErrorBit.testSPI = 0;
				DINT;
				testSpiObject.spiPort = 0;
				testSpiObject.pTestData = (uint8_t *) gCommTestData;
				testSpiObject.testDataSize = 8;
				testSpiObject.spiBitRateDivider = 4;
				testSpiObject.delayCount = 13;

				pTestSpi = (STL_TYPE1_SPI_TEST_spiTest_Handle) &testSpiObject;

				status = STL_TYPE1_SPI_TEST_testSpiLoopback(pTestSpi);

				EINT;
				if (status != SIG_SPI_TEST)
				{
					perErrorCode_st.perErrorBit.testSPI = 1;
					STL_FAIL_SAFE_failSafe();
				}
				gTestType = WAIT_FOR_TEST_CMD;

			break;

			case TEST_SCI: // start up test only

				// wait until FIFO is empty
				while (SciaRegs.SCIFFTX.bit.TXFFST != 0)
				{

				}
				EALLOW;
				GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Enable pull-up for GPIO28 (SCIRXDA)
				GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1;	// Enable pull-up for GPIO29 (SCITXDA)

				GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0; // disable GPIO28 for SCIRXDA operation
				GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0; // disable GPIO29 for SCITXDA operation
				EDIS;

				status = 0;
				perErrorCode_st.perErrorBit.testSCI = 0;
				DINT;
				testSciObject.sciPort = 0;
				testSciObject.pTestData = (uint8_t *) gCommTestData;
				testSciObject.testDataSize = 8;
				// set baud rate to 9600
				testSciObject.sciLowBitRate = 0x00E7;
				testSciObject.sciHighBitRate = 0x0001;
				testSciObject.delayCount = 11300;

				pTestSci = (STL_TYPE0_SCI_TEST_sciTest_Handle) &testSciObject;

				status = STL_TYPE0_SCI_TEST_testSciLoopback(pTestSci);

				// reconfigure the SCI port
				InitSciaGpio();
				SciaRegs.SCIFFTX.bit.SCIRST = 1;

				if (status != SIG_SCI_TEST)
				{
					perErrorCode_st.perErrorBit.testSCI = 1;
					STL_FAIL_SAFE_failSafe();
				}


				// Test SCI B

				testSciObject.sciPort = 1;
				EALLOW;
				GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // disable GPIO11 for SCIRXDC operation
				GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; // disable GPIO15 for SCIRXDC operation
				GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // disable GPIO19 for SCIRXDC operation
				GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; // disable GPIO23 for SCIRXDC operation
				GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // disable GPIO9 for SCITXDC operation
				GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; // disable GPIO14 for SCITXDC operation
				GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // disable GPIO18 for SCITXDC operation
				GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // disable GPIO22 for SCITXDC operation
				EDIS;

				status = STL_TYPE0_SCI_TEST_testSciLoopback(pTestSci);
				if (status != SIG_SCI_TEST)
				{
					perErrorCode_st.perErrorBit.testSCI = 1;
					STL_FAIL_SAFE_failSafe();
				}


				// Test SCI C

				testSciObject.sciPort = 2;
				EALLOW;
				GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 0; // disable GPIO62 for SCIRXDC operation
				GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 0; // disable GPIO63 for SCITXDC operation
				EDIS;

				EINT;
				status = STL_TYPE0_SCI_TEST_testSciLoopback(pTestSci);
				if (status != SIG_SCI_TEST)
				{
					perErrorCode_st.perErrorBit.testSCI = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;

			break;

			case TEST_I2C: // start up test only

				status = 0;
				perErrorCode_st.perErrorBit.testI2C = 0;
				DINT;
				testI2cObject.i2cPreScaler = 1;
				testI2cObject.i2cOffClockDivider = 44;
				testI2cObject.i2cOnClockDivider = 44;
				testI2cObject.delayCount = 710;

				pTestI2c = (STL_TYPE0_I2C_TEST_i2cTest_Handle) &testI2cObject;

				status = STL_TYPE0_I2C_TEST_testI2cLoopback(pTestI2c);

				EINT;
				if (status != SIG_I2C_TEST)
				{
					perErrorCode_st.perErrorBit.testI2C = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;

			break;

			case TEST_ECAP_APWM_MODE:

				IER &= 0x8000; // disable all interrupts except SPC detect (RTOS isr) = 0;
				status = 0;
				// half duty cycle
				testEcapApwmObject.testEcap = 5;
				testEcapApwmObject.inverseDutyCycle = 2;
				testEcapApwmObject.dutyCycleCount = 7500000;
				testEcapApwmObject.periodCount = 15000000;
				testEcapApwmObject.timeoutCount = 1071424;
				testEcapApwmObject.periodCompare = 1071411;
				pTestEcap =
						(STL_TYPE0_ECAP_TEST_ecapApwmTest_Handle) &testEcapApwmObject;

				perErrorCode_st.perErrorBit.testECAP = 0;
				DINT;

				status = STL_TYPE0_ECAP_TEST_testEcapApwmMode(pTestEcap);

				EINT;
				if (status != SIG_ECAP_APWM_TEST)
				{
					perErrorCode_st.perErrorBit.testECAP = 1;
					STL_FAIL_SAFE_failSafe();
				}


				// a third duty cycle
				testEcapApwmObject.testEcap = 2;
				testEcapApwmObject.inverseDutyCycle = 3;
				testEcapApwmObject.dutyCycleCount = 5000000;

				DINT;
				status = STL_TYPE0_ECAP_TEST_testEcapApwmMode(pTestEcap);
				EINT;
				if (status != SIG_ECAP_APWM_TEST)
				{
					perErrorCode_st.perErrorBit.testECAP = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;
				IER |= M_INT14; // enable timer ISR
			break;

			case TEST_OSCILLATOR:

				testOscObject.pwmChannel = 4;
				testOscObject.mepMin = 29;
				testOscObject.mepMax = 59;
				testOscObject.sfoDelay = 450;

				pTestOsc = (STL_OSCILLATOR_TEST_oscTestUsingSfo_Handle) &testOscObject;

				status = 0;
				perErrorCode_st.perErrorBit.testOSC = 0;

				status = STL_OSCILLATOR_TEST_testExtOscUsingSf0(pTestOsc);

				EINT;
				EALLOW;
				SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = gHrpwmenclkBackup;
				EDIS;
				if (status != SIG_OSC_TEST)
				{
					perErrorCode_st.perErrorBit.testOSC = 1;
					STL_FAIL_SAFE_failSafe();
				}


				gTestType = WAIT_FOR_TEST_CMD;

				break;

			case TEST_ADC:

				// Set ADC clock t0 25MHz = 150/3
				EALLOW;
				SysCtrlRegs.HISPCP.all = 7U;
				AdcRegs.ADCTRL1.bit.CPS = 0U;
				AdcRegs.ADCTRL3.bit.ADCCLKPS = 0U;
				EDIS;

				InitAdc();
				// connect pin A2 to 2.86 v
				// connect pin B2 to 1.257 v

				testAdcObject.pinACount = 3904;
				testAdcObject.pinBCount = 1716;
				testAdcObject.muxChannel = 2;
				testAdcObject.singleChannelSelect = 0;
				testAdcObject.delayCount = 5500;

				pTestAdc = (STL_TYPE2_ADC_TEST_adcTest_Handle) &testAdcObject;

				status = 0;
				perErrorCode_st.perErrorBit.testADC = 0;
				DINT;
				status = STL_TYPE2_ADC_TEST_testAdcInput(pTestAdc);
				EINT;
				if (status != SIG_ADC_TEST)
				{
					perErrorCode_st.perErrorBit.testADC = 1;
					STL_FAIL_SAFE_failSafe();
				}

				// connect pin B7 to 2.86 v
				// connect pin A7 to 1.257 v
				testAdcObject.pinACount = 1716;
				testAdcObject.pinBCount = 3904;
				testAdcObject.muxChannel = 7;
				status = 0;

				DINT;

				status = STL_TYPE2_ADC_TEST_testAdcInput(pTestAdc);

				EINT;
				if (status != SIG_ADC_TEST)
				{
					perErrorCode_st.perErrorBit.testADC = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;

				break;

			case TEST_EPWM:
				IER &= 0x8000; // disable all interrupts except SPC detect (RTOS isr) = 0;
				status = 0;
				perErrorCode_st.perErrorBit.testEPWM = 0;
				DINT;

				status = STL_TYPE0_EPWM_TEST_testEpwm();

				EINT;
				if (status != SIG_EPWM_TEST)
				{
					perErrorCode_st.perErrorBit.testEPWM = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;
				IER |= M_INT14; // enable timer ISR

				break;

			case TEST_CAN: // start up test only

				status = 0;
				perErrorCode_st.perErrorBit.testCAN = 0;
				DINT;

				status = STL_TYPE0_ECAN_TEST_testeCanLoopback(4, 7938, 1);

				EINT;
				if (status != SIG_ECAN_TEST)
				{
					perErrorCode_st.perErrorBit.testCAN = 1;
					STL_FAIL_SAFE_failSafe();
				}
				gTestType = WAIT_FOR_TEST_CMD;

			break;

			case TEST_PERIPHERAL_REGISTER: // start up test only

				status = 0;
				testPeriphRegisters.pRegisterStartAddress = (uint16_t *) 0x0CE2;
				testPeriphRegisters.pRegisterEndAddress = (uint16_t *) 0x0CF9;
				testPeriphRegisters.pTestPattern1 = pieRegistersTestPattern1;
				testPeriphRegisters.pTestPattern2 = pieRegistersTestPattern2;
				pPeriphRegisters = (STL_REGISTER_TEST_registerTest_Handle) &testPeriphRegisters;
				perErrorCode_st.perErrorBit.testPeripReg = 0;
				DINT;

				status = STL_REGISTER_TEST_testPeripheralRegisters(pPeriphRegisters);

				EINT;
				if (status != SIG_PERIPH_R_TEST)
				{
					perErrorCode_st.perErrorBit.testPeripReg = 1;
					STL_FAIL_SAFE_failSafe();
				}

				status = 0;
				// Disconnect pins from SPI A module
				EALLOW;
				GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // set as GPIO
				GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // set as GPIO
				GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // set as GPIO
				GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // set as GPIO
				EDIS;
				testPeriphRegisters.pRegisterStartAddress = (uint16_t *) 0x7040;
				testPeriphRegisters.pRegisterEndAddress = (uint16_t *) 0x704C;
				testPeriphRegisters.pTestPattern1 = spiRegistersTestPattern1;
				testPeriphRegisters.pTestPattern2 = spiRegistersTestPattern2;
				pPeriphRegisters =(STL_REGISTER_TEST_registerTest_Handle) &testPeriphRegisters;


				DINT;

				status = STL_REGISTER_TEST_testPeripheralRegisters(pPeriphRegisters);

				EINT;
				if (status != SIG_PERIPH_R_TEST)
				{
					perErrorCode_st.perErrorBit.testSPI = 1;
					STL_FAIL_SAFE_failSafe();
				}

				gTestType = WAIT_FOR_TEST_CMD;
			break;

			case END_TEST:

				gTestType = WAIT_FOR_TEST_CMD;
			break;

			default:
				gTestType = WAIT_FOR_TEST_CMD;
			break;


        }
}// end of STL_TEST_REPORT_testDevice function

Now, program falls into illegal_isr after jumping application.

When I got binary output of application from CCS. It is converted like Project.x01 not .bin extension but, when I check this file I saw there is no difference between .x01 extension and .hex output, so I though this extension is ok.

Btw, I deleted PAGE 1 and copied everything in PAGE 1 to PAGE 0. But .bin output still is not  being converted.

Anyway, the picture above belogns to .x01 binary output in a hex converter program on PC.

I checked how I program flash memory of DSP and saw the byte order is same like here.

I really do not know why program jumps illegal isr. 

This is memory configuration about how application and calibration data are allocated in memory.

Do you see any problem here ?

UPDATE:

As seen in the picture, when program falls into illegal isr, debugger screns show there may a problem at 0x000000. If this make sense, as I mentioned like before

both application and bootloader codes have own reset handler and vector handler right ? I do not know how I am gonna modify linker for this.

Now, program falls into illegal_isr after jumping application.

When I got binary output of application from CCS. It is converted like Project.x01 not .bin extension but, when I check this file I saw there is no difference between .x01 extension and .hex output, so I though this extension is ok.

Btw, I deleted PAGE 1 and copied everything in PAGE 1 to PAGE 0. But .bin output still is not  being converted.

Anyway, the picture above belogns to .x01 binary output in a hex converter program on PC.

I checked how I program flash memory of DSP and saw the byte order is same like here.

I really do not know why program jumps illegal isr. 

This is memory configuration about how application and calibration data are allocated in memory.

Do you see any problem here ?

UPDATE:

As seen in the picture, when program falls into illegal isr, debugger screns show there may a problem at 0x000000. If this make sense, as I mentioned like before

both application and bootloader codes have own reset handler and vector handler right ? I do not know how I am gonna modify linker for this.

After Bootloader branched to the app, it executes addresses which stored in memory in order then comes last adress in the memory so after this

falls trap functions as you see. As if appication in the flash are not seen as a code block.

Any help :( I got stuck at %99 of bootloading process. Lol

Hi, 

What is the entry point of the application? . After flashing the application , how are you branching to the entry point of the application to run it?

Can you try loading the symbols in CCS and figure out if the application is programmed successfully? 

Best Regards

Siddharth

Hi,

I used these variants of branching

//BL_CallApplication();
//((void (*)(void))APP_START_ADDRESS)();
((void(*)(void))((uint32_t *)APP_START_ADDRESS))(); /*the current one*/
//asm( " LB 0x300000 " );

BL_CallApplication is a wrapper that calls these asm code

	.def _jumpToAppEntry
	.text
_jumpToAppEntry:
	SETC INTM;
	ZAPA;
	MOV @SP,#0;
	PUSH ACC;
	PUSH AL;
	MOV AL, #0x0a08;
	PUSH AL;
	MOVL XAR7, #0x00300000;
	PUSH XAR7;
	POP RPC;
	POP ST1;
	POP ST0;
	POP IER;
	POP DBGIER;
	LRETR;

Siddharth Deshpande said:

Can you try loading the symbols in CCS and figure out if the application is programmed successfully? 

I do not understand the meaning of loading symbols in CCS.

I opened the binary file on .hex editor and memory viewer on CCS while debugging and compare each other and byte orders

was same, this is the way that how I figured out it.

Hi, 

After flashing the application, you can connect using CCS and then use "load symbols" to load the symbols of your application. 

After this, you can issue a reset in CCS and observer the behavior.

Best Regards

Siddharth

I did something like that : I downloaded application to MCU standalone with the linker  which its BEGIN points last two address of FLASHG ( I configured onlly sectorH and sectorG for app allocation). Program works as intended but whenever I reset the CPU and debugged in dissasembly window and this time, I saw the  application jumped  0x307FFE but fails because of there is no code related with CodeStartBranch.asm. I really don't understand this.

Secondly, I runned bootloader code and downloaded same application with same linker above and I noticed this time it jumped last two address of FLASHG but again there was no any code there as in the picture below.

I have to clarify some points before moving forward.

1. If I want to allocate FLASHA for Bootloader, where should I modify the linker ?

/*
//###########################################################################
//
// FILE:	F28335.cmd
//
// TITLE:	Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $
// $Release Date: June 8, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file, 
// add the header linker command file directly to the project. 
// The header linker command file is required to link the
// peripheral structures to the proper locations within 
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//   
// For BIOS applications add:      DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add:   DSP2833x_Headers_nonBIOS.cmd    
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F28335  
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

    Notes: 
          Memory blocks on F28335 are uniform (ie same
          physical memory) in both PAGE 0 and PAGE 1.  
          That is the same memory region should not be
          defined for both PAGE 0 and PAGE 1.
          Doing so will result in corruption of program 
          and/or data. 
          
          L0/L1/L2 and L3 memory blocks are mirrored - that is
          they can be accessed in high memory or low memory.
          For simplicity only one instance is used in this
          linker file. 
          
          Contiguous SARAM memory blocks can be combined 
          if required to create a larger memory block. 
 */


MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   ZONE0       : origin = 0x004000, length = 0x001000     /* XINTF zone 0 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   RAML2_1     : origin = 0x00A000, length = 0x000AA8     /* on-chip RAM block L2 */
   PC_TEST_1   : origin = 0x00AAA8, length = 0x000004     /* PC test function 1 */
   RAML2_2     : origin = 0x00AAAC, length = 0x000554     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */ 
   ZONE7A      : origin = 0x0200000, length = 0x00FC00    /* XINTF zone 7 - program space */ 
   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF_1    : origin = 0x310000, length = 0x005554     /* on-chip FLASH */
   PC_TEST_2   : origin = 0x315554, length = 0x000004     /* PC test function 2 */
   FLASHF_2    : origin = 0x315558, length = 0x002AA8     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */   
   FLASHC_1    : origin = 0x328000, length = 0x002AA8     /* on-chip FLASH */
   PC_TEST_3   : origin = 0x32AAA8, length = 0x000004     /* PC test function 3 */
   FLASHC_2    : origin = 0x32AAAC, length = 0x005554     /* on-chip FLASH */   
   FLASHA      : origin = 0x338000, length = 0x007E80     /* on-chip FLASH */
   
   CRC_TABLE   : origin = 0x33FE80, length = 0x000100     /* Table to hold 32 golden CRC values */
   
   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400     /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
   
   IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */  
   FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */        
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L1 */
   RAML5       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L1 */
   RAML6       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L1 */
   RAML7       : origin = 0x00F000, length = 0x001000     /* on-chip RAM block L1 */
   ZONE7B      : origin = 0x20FC00, length = 0x000400     /* XINTF zone 7 - data space */
   FLASHB      : origin = 0x330000, length = 0x008000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/ 
 
SECTIONS
{
 
   /* Allocate program areas: */
   .cinit              : > FLASHC_1,      PAGE = 0
   .pinit              : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,    PAGE = 0
   .text               : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,       PAGE = 0
   codestart           : > BEGIN       PAGE = 0


   Flash28_API:
   {
        -l Flash28335_API_V210.lib(.econst)
        -l Flash28335_API_V210.lib(.text)
   }
   						LOAD = FLASHD,
                       	RUN = RAML0,
                       	LOAD_START(_Flash28_API_LoadStart),
                       	LOAD_END(_Flash28_API_LoadEnd),
                       	RUN_START(_Flash28_API_RunStart),
                       	PAGE = 0

   ramfuncs            : LOAD = FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0


    psa_crc             : LOAD =  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = RAML0,
                         LOAD_START(_PSA_CRCLoadStart),
                         LOAD_END(_PSA_CRCLoadEnd),
                         RUN_START(_PSA_CRCRunStart),
                         RUN_END(_PSA_CRCRunEnd),
						 LOAD_SIZE(_PSA_CRCLoadSize),
						 PAGE = 0
                         
   pc_test_section_1   : LOAD =  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,
                         RUN = PC_TEST_1,
                         LOAD_START(_PC_Test1LoadStart),
                         LOAD_END(_PC_Test1LoadEnd),
                         RUN_START(_PC_Test1RunStart),
                         RUN_END(_PC_Test1RunEnd),
						 LOAD_SIZE(_PC_Test1LoadSize),
						 PAGE = 0





   pc_test_section_2   : > PC_TEST_2, PAGE = 0
   pc_test_section_3   : > PC_TEST_3, PAGE = 0

   STL_Test_utility  : > RAMM1, PAGE = 1
   STL_psa_crc_vars  : > RAMM1, PAGE = 1
   STL_crc_test_data : > FLASHB, PAGE = 1
   
   csmpasswds          : > CSM_PWL     PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0

   STL_CRC_calc   : > FLASHA, PAGE = 0
   STL_CRC_TABLE  : > CRC_TABLE, PAGE = 0


   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML4       PAGE = 1
   .esysmem            : > RAMM1       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,      PAGE = 0
   .switch             : >>  FLASHG | FLASHF_1 | FLASHF_2 |   FLASHC_1 | FLASHC_2,      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : >>  FLASHG | FLASHF_1 | FLASHF_2 |  FLASHC_1 | FLASHC_2,      PAGE = 0                  /* Math Code */
   IQmathTables     : > IQTABLES,  PAGE = 0, TYPE = NOLOAD 
   
   /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the 
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM 
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 
   {
   
              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
   
   }
   */
   
   FPUmathTables    : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 
         
   /* Allocate DMA-accessible RAM sections: */
   DMARAML4         : > RAML4,     PAGE = 1
   DMARAML5         : > RAML5,     PAGE = 1
   DMARAML6         : > RAML6,     PAGE = 1
   DMARAML7         : > RAML7,     PAGE = 1
   
   /* Allocate 0x400 of XINTF Zone 7 to storing data */
   ZONE7DATA        : > ZONE7B,    PAGE = 1

   /* .reset is a standard section used by the compiler.  It contains the */ 
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */ 
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
   
   /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
   .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

2. If I want to allocate FLASHH and FLASHG sectors  where should I modify the linker ?

Please show me places where I have to modify in the linker above.

I thought I could not allocate whole memory sectors for app. Because sectors are not sorted consecutively due to the some safety modules allocate some memory blocks of sections. This can bee seen in the linker file above.

4. In threads you shared, says I have to modify BEGIN section of application linker which is linked an .asm code in CCS files.

  I configured my bootloader in the way it will flash application from starting address of FLASH H through FLASHG and  I configured BEGIN section of application

 BEGIN       : origin = 0x30FFFE, length = 0x000002 (last two adress of FLASHG)

FLASHG      : origin = 0x308000, length = 0x007FFE (old 0x008000)

Do I have to change FLASHG layout as above in the bootloader linker too ?

I allocated last two adress for code brancing .asm code but how the program writes bin files of .asm codes to thesee adresses ?

Because I did not write anything there. Just allocated.

5. Do I have to modify anything in .asm code ?.

any help ?