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Hi all!
As mentioned in the title I want to read from 2 SPI slaves(ADC) simultaneously. I didnt go deeper but it looks possible by combining SPI and CLB(Configurable logic block) peripherals. With SPI I have CLK, CS and MISO pins and i want to add second MISO. So interface pins will be like CLK, CS, MISO1 and MISO2 and it is high speed communication(48 MHz).
My question is if is there any example or reference design regarding to my issue? I will soon start to read reference manual and go deeper with the SPI and CLB modules respectively. However if there is specific examples or references addresee to my issue that would ease my development process and reduce development time and would be appreaciated. 
Thanks in advance.
I scratched soemthing for you with paint. I hope you understand now better. It is a migration FPGA to DSP. SPI CLK is 48MHz.
I do not have an example. But would be glad to review your work once you put it together. The SPI CLK can be used in the CLB module as a boundary IN.
You can use this input as the ENABLE signal of the COUNTER module in SERIALIZER mode.
Nima
