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TMS320F280023: ADC INTERRUPT TMS320F280023

SIB CHAKRABARTI
Prodigy 50 points
Part Number: TMS320F280023

Page 86 of spruin7a.pdf says:

(1) INT1.1, INT10.1, INT10.2, INT10.3. INT10.4.

(2) INT1.3, INT10.9, INT10.10, INT10.11, INT10.12.

are the interrupts from ADC that can trigger CPU.

However, page 1507 of the same document says ADC can issue ADCINT1, ADCINT2, ADCINT3, ADCINT4 to PIE.

Please clarify the confusion.

  • 0
    TI__Guru 60865 points

    Hi Sib,

    There are two ADC modules, ADC-A and ADC-C on the device, each of which has 4 interrupt lines to the PIE.  

    Table 3-3. "Pie Channel Mapping" shows the full mapping for device, while Figure 15-7. "ADC EOC Interrupts" is from the perspective of a single ADC instance. 

    Note: Typically you'd be running the two ADCs in parallel to get simultaneous voltage conversions (or just to process the needed channels in parallel).  In this case, you can just pick one ADC to generate the ADC interrupt.  e.g. if the ADC setup looks like:

    *ADC-A: SOC0 = Channel A3, SOC1 = Channel A0, SOC2 - Channel A5 (all 3 SOCs triggered by ePWM1A)

    *ADC-C: SOC0 = Channel C9, SOC1 = Channel C1, SOC2 - Channel C2 (all 3 SOCs triggered by ePWM1A)

    Then SOC2 from either ADC-A or ADC-C, triggering ADCINT1 on that ADC, triggering the ISR through the PIE, to go collect all 6 samples is fine (no need to trigger a separate ISR for each ADC)

  • 0 in reply to Devin Cottier
    Prodigy 50 points

    thanks Devin for explaining, this co-relation does NOT exist in the document !

    One more question:

    I saw 16 numbers of ADCRESULTS  registers for ADC-A and ADC-C, totalling 32 registers. However, this processor TMS320F280023 has only 16 PINs for ADC inputs. Does it mean that only 16 registers are used from both ADC-A and ADC-C at a time and the rest 16 are redundant ?

  • 0 in reply to SIB CHAKRABARTI
    TI__Guru 60865 points

    Hi Sib,


    The additional result register can be used in a variety of use cases.   For instance, the same channel can be sampled multiple times back-to-back and then the results averaged together (oversampling).  "Burst Mode" also allows the additional result registers to be used as a circular buffer and/or for different channels to be sampled each time the trigger is received.