TMS320F280049C: ADC noise

Hi Evan,

Thanks for detailed description of the issue with excellent supporting data!

Base on your report, it looks like some channels have good performance (single-modal distribution, maybe 4-6 codes wide across 200k conversions, 0.5-1 LSBs standard deviation) so I think the ADC is probably fundamentally working well.  It is still always worth sanity checking the VDDA voltage, the device SYSCLK, the SYSCLK to ADCCLK divider, and the VREFHI/LO voltage and connection.  

I haven't fully traced through all the layout, but I think overall it looks very good.  

So one key piece of information we are still missing is (1) how long is the S+H time for these channels - set by the ACQPS setting of the ADC SOC configuration (2) how fast are you sampling each channel and (3) what gets sampled immediately before the channels that are having issues.  This is to determine if there is some issue with inadequate settling time or memory cross-talk.  See https://www.ti.com/lit/an/spract6/spract6.pdf and https://www.ti.com/lit/an/spracv0/spracv0.pdf for some design guidelines for determining appropriate S+H time or sample rate on a given channel.  

For instance, it looks like the INA181 has ~300kHz BW, which might be on the slower side for driving the ADC and then there is a series 1kohm resistor which might further slow down input settling.  As a quick experiment, you might try increasing the S+H for that channel and/or replacing the 1kohm resistor with say 10ohms. 

I'd also caution against using a battery as a test voltage; I haven't seen this actually produce a nice stable low-noise voltage.  Instead, use a laboratory function generator with minimal length (and shielded where possible) cabling.  The https://www.ti.com/tool/PSIEVM is also a great tool for getting a low-noise DC or AC test signal.  

Hi devin

Thanks for your response

During my test using C2000Ware MotorControlSDK 3.03 , I use it's original setting for : SYSCLK 100MHz, ADCLK divider is 2, but i increase the ADC Tsh to be 1790nS (ADC Tsh+Teoc = 2000nS), and ADC sampling rate is 10KHz (USER_PWM_FREQ_kHz = 20 and USER_NUM_PWM_TICKS_PER_ISR_TICK = 2)

INA181A2 BW is 210KHz, that is related to 10.5MHz UGBW, i can't drive the ADC very fast by using 10ohm resistor, from TI's precision labs training video : TIPL4406 The Math Behind the R-C Component Selection, by using TMS320C28004pc SAR ADC  Csh 7.5pF and Rsh 860Ohm, we get Cfilt = 150pF and Rfilt 390Ohm 345nS Tsh (9.9MHz UGBW needed). Regarding 1Kohm series resistor is only for lowering the BW (and 1790nS Tsh is still enough for 1Kohm Rfilt) and And the simulation result by using TINA s/w is as in figure 14 & 15 (please refer to my new attachment file), it can be seen that either 1Kohm or 390ohm Rfilt and Tsh 1790nS give <0.5LSB error)

From my previous report, actually i don't satisfy with the result, even the StDev is around 0.5-1 (5-9 error code from 200k conversion) because  DC voltage is directly applied to ADC input, actually with this condition i expect no error code . And even while trying to drive ADC from INA181A2, the  histogram become bimodal distribution.

Regarding battery supply, actually i only want to make sure supplying the system with clean DC source, since i also add 1000uF solid polymer cap parallel with the battery.

Then, i conduct some more experiment, , you can refer to figure 10 - 13 from my new attachment file. The bimodal distribution from INA181A2 driving ADC, now disappear and also better StDev as well, from 2.3 (14 - 15 error code), down to 1.4 (10 - 11 error code) , by doing below experiments :

1. Merge INA Vcc and ADC Vcc as in fig 10. There is only 3V3 LDO, directly supply from DC supply or battery, there is no difference result by using or not using 470uF solid polymer cap.

2. Merge INA Vcc and ADC Vcc as in fig 11. There is LDO or Buck converter step down from 15V from DC supply, there is no difference result between LDO and Buck converter, and there is also no significant difference by using or not using 470uF solid polymer cap.

3. INA supplied by 5V (LDO or Buck) and ADC supplied by 3V3 LDO, as in figure 12. 470uF between 5V step down  and 3V3 LDO is a must to get improvement. There is no difference between LDO and buck for 15V to 5V step down.

Do you think separate Dgnd and Agnd ground plane can improve the ADC noise performance? From many literature [FAQ] PCB Layout Guidelines and Grounding Recommendations for High-Resolution ADCs - Data converters forum - Data converters - TI E2E support forums , MT-031: Grounding Data Converters and Solving the Mystery of "AGND" and "DGND" (analog.com) they don't suggest this idea (2 plane), even TMS320C24009 launch board also use single ground plane for Agnd and Dgnd, but instead of splitting the Dgnd and agnd ground plane, they suggest to separate the digital and analog circuit (which is actually i have made in my board), and connect the dgnd and agnd with very low impedance plane at ADC (Dgnd pin of ADC should be connected to Agnd plane as well). But this raise another question in my mind, since i use integrated ADC and MCU. To which ground pin does C280049C's ADC digital circuit is connected to? Is it connected to VSSA as well or  VSS?

Thank you and best regards

evan

Sorry i forgot the attachment, here it is : TMS320F28004 ADC noise result R1.pdf

Hi Evan,

On the split analog / digital ground planes: this can be a good design choice, but if you do it incorrectly you can also make noise much much worse.  One possibility is to split the planes, make sure to route all signals with respect to their new planes (analog over the analog plane, digital over the digital plane) but then remove the split at the end.  This gets you physical separation of the analog and digital signals and their return paths, which will get you most of the benefit without risk of causing issues (issues arise if you route a signal over one plane, but really it should be referenced to the other plane - or if you accidentally route signals over the split in the plane).  

Internally, the digital portion of the ADC (wrapper, logic, etc) is referenced to the digital ground VSS while the analog circuits (ADC input mux, S+H, converter, etc.) are referenced to the analog ground, VSSA.  If you do split the planes you would generally join them at a single point directly under the device.

You might look out for issues with low-frequency noise in your battery source.  Does the standard deviation improve if you take a shorter capture (say only a couple 100 codes?).  

It is good to see that you are making some improvement. One additional question on the INA input: it looks like you shorted the pins together, but do you also drive a DC voltage here, or just let the input float?  If float, is it possible that whatever voltage it is floating to is outside of the common mode range (or that the voltage floating around is otherwise causing some input noise)?     

Hi devin

Regarding your suggestion : split the plane initially and route digital and analog with respect to their gnd plane and then connect those 2 planes at the bottom of C2000, 

1. Do you mean, at the end there will be only 1 solid plane (no cut, / separation ), but since at PCB routing process, the plane are initially separated, the trace and components are placed and route and the top of each dedicated ground plane as in figure on the left, OR Agnd and Dgnd plane are physically keep separated, but, combined together at the bottom of ADC / C2000 MCU as this figure on right. Which one is correct ?

2. If you mean,  the two gnd plane are keep "separated", but combined together at the bottom of ADC (as figure on the right), there will be a ground loop, because at the bulk cap, we also combined these 2 planes, or should we only connect one of them?

<Devin>  it looks like you shorted the pins together, but do you also drive a DC voltage here, or just let the input float?  If float, is it possible that whatever voltage it is floating to is outside of the common mode range (or that the voltage floating around is otherwise causing some input noise)?

<Evan> Actually i do both : just shorted the 2 input and keep them floating (only depend on the INA CMRR)  and connect the shorted pins to ground, Either noise histogram are or StDev are very similar, around 1.42.

Thank you and best regards

evan

Hi Evan,

Yes, the recommendation to split the ground planes, route the signals, but then at the end use a combined plane will result in something like your picture on the left.  There will be only one unified ground plane with no cuts. Ultimately this is just physically separating the analog and digital circuits with the additional steps of initially adding a hard boundary. While this is not optimal, this will avoid the risk of making things worse by adding cuts in the ground that cause some poorly routed signals to take very long out-of-the way return paths.

In the second case, where the grounds are joined at a single point ("star connection") we would want to fully cut the plane and join only at a single point (usually using a 0-ohm resistor or maybe an EMI bead).  We would still certainly want the return currents to flow, as much as possible, through their own planes without even needing the cut (physical separation as in the previous solution).    However, as you point out, it is certainly possible to introduce ground loops in this situation, particularly as the system/PCB become more complex.  For instance, it can be hard to maintain a single ground point if there are cable connections or daughter card connections that carry mixed analog and digital signals (or if the controller board itself is a daughter card, perhaps to a board with the power electronics to be controlled).