TMS320F28388S: Flash code does not run after power reset

Hi Alexis,

Is this your custom project or an example in C2000Ware? If it is an example, please send us the path so that we can check with corresponding expert to try that.

If the example works after programming it but not after power cycle:

1) Could you check if there is an ECC error?  Gel file disables ECC-evaluation and hence you may not notice the error when the debugger is connected (assuming the ECC error happened before the flash initialization routine).

2) Could you check if there is a toggle on the XRSn when it did not work?  Maybe a watchdog reset is occurring?  Again, the gel file disables the watchdog and hence asking you to check that.

Also, this FAQ may help: How to modify an application from RAM configuration to Flash configuration?: https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/878674 

Thanks and regards,
Vamsi

Hi Vamsi, thank you for your help.

I started the project using the example: gpio_ex2_toggle.c from C:\ti\C2000Ware_4_00_00_00\driverlib\f2838x\examples\c28x\gpio

As it is intended for a 2838D with the XDS100V2 I changed the target config for XDS100V3 et Device F2838S. Then I also changed the Sysconfig for the F2838S: and choose my GPIO.

That pretty much it, really simple and straightforward.

So when I try to program it in flash, the console returns:

C28xx_CPU1: GEL Output: 
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output: 
... DCSM Initialization Start ... 
C28xx_CPU1: GEL Output: 
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output: 
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)

After programming, the code runs on the F28388 I see the LEDs, but does not run if I do a power reset.

I probed the XRSn and it stayed high all the time during and after the programming sequence.

Alexis

I attached my project if it can help.

Blink_LED.zip

Hi Alexis,

Thank you for the info.  EtherSNACKS_Blink_LED.map in CPU1_FLASH folder is the map file for your application - correct?  Please confirm.

I requested our team to try this example's flash build config - they will get back to you. 

Regards,
Vamsi

Yes or Blink_LED.map, it is the same file, I just renamed the project:

Hi Alexis,

I tried running your project on a F28388D controlcard. I updated the GPIO pins to match the LED pins used in my board and the application seems to be running even after a power on reset.

Regards,

Veena

Hi Veena, I also tried on the F28388D controlcard and it was working.

I dug a little bit further and discovered it is actually booting on FLASH sometimes, but 80% of the time it does not.

I tried with another new board and it behaves the same.

What I observed:

1. I flash my program in Flash, keep the JTAG connected on the board (XDS100V3 Olimex)
2. My program is running
3. Power cycle the power supply
4. The uC does not boot in flash
5. Disconnect and reconnect the JTAG from the board
6. Power cycle the power supply
7. The uC boot in flash 
8. Power cycle the power supply
9. The uC does not boot in flash
10. Disconnect and reconnect the JTAG from the board
11. Power cycle the power supply
12. The uC boot in flash
13. ...

So there might be something with the boot sequence and timing issue or with the JTAG pins.

 My schematic is pretty much the same as the ControlCard, I am using the TPS62410DRCR for the 3V3 and 1V2 instead of the TPS62420DRCR (was out of stock everywhere)

And I am using two supervisors to monitor the voltages, same as the control card:

And the two GPIO are tied to 3V3 to boot in flash:

I will try to probe the MCU_XRSn and make sure everything is as expected:

Other than that, let me know if you have any suggestions.

Alexis

From a software prospective, is it possible a small piece of code is missing somewhere and prevent me to boot in flash?

Here is the 2838x_FLASH_lnk_cpu1.cmd I am currently using

MEMORY
{
   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN            : origin = 0x080000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD       : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD0            : origin = 0x00C000, length = 0x000800
   RAMD1            : origin = 0x00C800, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMGS0           : origin = 0x00D000, length = 0x001000
   RAMGS1           : origin = 0x00E000, length = 0x001000
   RAMGS2           : origin = 0x00F000, length = 0x001000
   RAMGS3           : origin = 0x010000, length = 0x001000
   RAMGS4           : origin = 0x011000, length = 0x001000
   RAMGS5           : origin = 0x012000, length = 0x001000
   RAMGS6           : origin = 0x013000, length = 0x001000
   RAMGS7           : origin = 0x014000, length = 0x001000
   RAMGS8           : origin = 0x015000, length = 0x001000
   RAMGS9           : origin = 0x016000, length = 0x001000
   RAMGS10          : origin = 0x017000, length = 0x001000
   RAMGS11          : origin = 0x018000, length = 0x001000
   RAMGS12          : origin = 0x019000, length = 0x001000
   RAMGS13          : origin = 0x01A000, length = 0x001000
   RAMGS14          : origin = 0x01B000, length = 0x001000
   RAMGS15          : origin = 0x01C000, length = 0x000FF8
//   RAMGS15_RSVD     : origin = 0x01CFF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   /* Flash sectors */
   FLASH0           : origin = 0x080002, length = 0x001FFE  /* on-chip Flash */
   FLASH1           : origin = 0x082000, length = 0x002000  /* on-chip Flash */
   FLASH2           : origin = 0x084000, length = 0x002000  /* on-chip Flash */
   FLASH3           : origin = 0x086000, length = 0x002000  /* on-chip Flash */
   FLASH4           : origin = 0x088000, length = 0x008000  /* on-chip Flash */
   FLASH5           : origin = 0x090000, length = 0x008000  /* on-chip Flash */
   FLASH6           : origin = 0x098000, length = 0x008000  /* on-chip Flash */
   FLASH7           : origin = 0x0A0000, length = 0x008000  /* on-chip Flash */
   FLASH8           : origin = 0x0A8000, length = 0x008000  /* on-chip Flash */
   FLASH9           : origin = 0x0B0000, length = 0x008000  /* on-chip Flash */
   FLASH10          : origin = 0x0B8000, length = 0x002000  /* on-chip Flash */
   FLASH11          : origin = 0x0BA000, length = 0x002000  /* on-chip Flash */
   FLASH12          : origin = 0x0BC000, length = 0x002000  /* on-chip Flash */
   FLASH13          : origin = 0x0BE000, length = 0x001FF0  /* on-chip Flash */
//   FLASH13_RSVD     : origin = 0x0BFFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   CPU1TOCPU2RAM   : origin = 0x03A000, length = 0x000800
   CPU2TOCPU1RAM   : origin = 0x03B000, length = 0x000800
   CPUTOCMRAM      : origin = 0x039000, length = 0x000800
   CMTOCPURAM      : origin = 0x038000, length = 0x000800

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800

   RESET            : origin = 0x3FFFC0, length = 0x000002
}

SECTIONS
{
   codestart           : > BEGIN, ALIGN(8)
   .text               : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(8)
   .cinit              : > FLASH4, ALIGN(8)
   .switch             : > FLASH1, ALIGN(8)
   .reset              : > RESET, TYPE = DSECT /* not used, */
   .stack              : > RAMM1

#if defined(__TI_EABI__)
   .init_array      : > FLASH1, ALIGN(8)
   .bss             : > RAMLS5
   .bss:output      : > RAMLS3
   .bss:cio         : > RAMLS5
   .data            : > RAMLS5
   .sysmem          : > RAMLS5
   /* Initalized sections go in Flash */
   .const           : > FLASH5, ALIGN(8)
#else
   .pinit           : > FLASH1, ALIGN(8)
   .ebss            : > RAMLS5
   .esysmem         : > RAMLS5
   .cio             : > RAMLS5
   /* Initalized sections go in Flash */
   .econst          : >> FLASH4 | FLASH5, ALIGN(8)
#endif

   ramgs0 : > RAMGS0, type=NOINIT
   ramgs1 : > RAMGS1, type=NOINIT
   
   MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
   MSGRAM_CPU_TO_CM    : > CPUTOCMRAM, type=NOINIT
   MSGRAM_CM_TO_CPU    : > CMTOCPURAM, type=NOINIT

   /* The following section definition are for SDFM examples */
   Filter_RegsFile  : > RAMGS0
   Filter1_RegsFile : > RAMGS1, fill=0x1111
   Filter2_RegsFile : > RAMGS2, fill=0x2222
   Filter3_RegsFile : > RAMGS3, fill=0x3333
   Filter4_RegsFile : > RAMGS4, fill=0x4444
   Difference_RegsFile : >RAMGS5, fill=0x3333

   #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = FLASH3,
                        RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(8)
   #else
       .TI.ramfunc : {} LOAD = FLASH3,
                        RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_SIZE(_RamfuncsLoadSize),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        RUN_SIZE(_RamfuncsRunSize),
                        RUN_END(_RamfuncsRunEnd),
                        ALIGN(8)
   #endif

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

And the .map:

******************************************************************************
             TMS320C2000 Linker PC v21.6.0                     
******************************************************************************
>> Linked Tue Feb  8 12:50:22 2022

OUTPUT FILE NAME:   <adc_ex1_soc_software.out>
ENTRY POINT SYMBOL: "code_start"  address: 00080000


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  BOOT_RSVD             00000002   000001af  00000000  000001af  RWIX
  RAMM0                 000001b1   0000024f  00000000  0000024f  RWIX
  RAMM1                 00000400   000003f8  000003f8  00000000  RWIX
  RAMLS0                00008000   00000800  0000012d  000006d3  RWIX
  RAMLS1                00008800   00000800  00000000  00000800  RWIX
  RAMLS2                00009000   00000800  00000000  00000800  RWIX
  RAMLS3                00009800   00000800  00000000  00000800  RWIX
  RAMLS4                0000a000   00000800  00000000  00000800  RWIX
  RAMLS5                0000a800   00000800  0000000b  000007f5  RWIX
  RAMLS6                0000b000   00000800  00000000  00000800  RWIX
  RAMLS7                0000b800   00000800  00000000  00000800  RWIX
  RAMD0                 0000c000   00000800  00000000  00000800  RWIX
  RAMD1                 0000c800   00000800  00000000  00000800  RWIX
  RAMGS0                0000d000   00001000  00000000  00001000  RWIX
  RAMGS1                0000e000   00001000  00000000  00001000  RWIX
  RAMGS2                0000f000   00001000  00000000  00001000  RWIX
  RAMGS3                00010000   00001000  00000000  00001000  RWIX
  RAMGS4                00011000   00001000  00000000  00001000  RWIX
  RAMGS5                00012000   00001000  00000000  00001000  RWIX
  RAMGS6                00013000   00001000  00000000  00001000  RWIX
  RAMGS7                00014000   00001000  00000000  00001000  RWIX
  RAMGS8                00015000   00001000  00000000  00001000  RWIX
  RAMGS9                00016000   00001000  00000000  00001000  RWIX
  RAMGS10               00017000   00001000  00000000  00001000  RWIX
  RAMGS11               00018000   00001000  00000000  00001000  RWIX
  RAMGS12               00019000   00001000  00000000  00001000  RWIX
  RAMGS13               0001a000   00001000  00000000  00001000  RWIX
  RAMGS14               0001b000   00001000  00000000  00001000  RWIX
  RAMGS15               0001c000   00000ff8  00000000  00000ff8  RWIX
  CMTOCPURAM            00038000   00000800  00000000  00000800  RWIX
  CPUTOCMRAM            00039000   00000800  00000000  00000800  RWIX
  CPU1TOCPU2RAM         0003a000   00000800  00000000  00000800  RWIX
  CPU2TOCPU1RAM         0003b000   00000800  00000000  00000800  RWIX
  CANA_MSG_RAM          00049000   00000800  00000000  00000800  RWIX
  CANB_MSG_RAM          0004b000   00000800  00000000  00000800  RWIX
  BEGIN                 00080000   00000002  00000002  00000000  RWIX
  FLASH0                00080002   00001ffe  00000000  00001ffe  RWIX
  FLASH1                00082000   00002000  00001444  00000bbc  RWIX
  FLASH2                00084000   00002000  00000000  00002000  RWIX
  FLASH3                00086000   00002000  0000012d  00001ed3  RWIX
  FLASH4                00088000   00008000  0000001c  00007fe4  RWIX
  FLASH5                00090000   00008000  000003ac  00007c54  RWIX
  FLASH6                00098000   00008000  00000000  00008000  RWIX
  FLASH7                000a0000   00008000  00000000  00008000  RWIX
  FLASH8                000a8000   00008000  00000000  00008000  RWIX
  FLASH9                000b0000   00008000  00000000  00008000  RWIX
  FLASH10               000b8000   00002000  00000000  00002000  RWIX
  FLASH11               000ba000   00002000  00000000  00002000  RWIX
  FLASH12               000bc000   00002000  00000000  00002000  RWIX
  FLASH13               000be000   00001ff0  00000000  00001ff0  RWIX
  RESET                 003fffc0   00000002  00000000  00000002  RWIX


SECTION ALLOCATION MAP

 output                                  attributes/
section   page    origin      length       input sections
--------  ----  ----------  ----------   ----------------
codestart 
*          0    00080000    00000002     
                  00080000    00000002     f2838x_codestartbranch.obj (codestart)

.cinit     0    00088000    0000001c     
                  00088000    00000009     (.cinit..data.load) [load image, compression = lzss]
                  00088009    00000001     --HOLE-- [fill = 0]
                  0008800a    00000006     (__TI_handler_table)
                  00088010    00000004     (.cinit..bss.load) [load image, compression = zero_init]
                  00088014    00000008     (__TI_cinit_table)

.reset     0    003fffc0    00000000     DSECT

.stack     0    00000400    000003f8     UNINITIALIZED
                  00000400    000003f8     --HOLE--

.init_array 
*          0    00082000    00000000     UNINITIALIZED

.bss       0    0000a80a    00000001     UNINITIALIZED
                  0000a80a    00000001     adc_ex1_soc_software.obj (.bss)

.data      0    0000a800    0000000a     UNINITIALIZED
                  0000a800    00000006     rts2800_fpu64_eabi.lib : exit.c.obj (.data)
                  0000a806    00000002                            : _lock.c.obj (.data:_lock)
                  0000a808    00000002                            : _lock.c.obj (.data:_unlock)

.const     0    00090000    000003ac     
                  00090000    00000098     driverlib.lib : flash.obj (.const:.string)
                  00090098    00000097                   : gpio.obj (.const:.string)
                  0009012f    00000001     --HOLE-- [fill = 0]
                  00090130    00000097                   : sysctl.obj (.const:.string)
                  000901c7    00000001     --HOLE-- [fill = 0]
                  000901c8    00000094                   : dcc.obj (.const:.string)
                  0009025c    00000079     adc_ex1_soc_software.obj (.const:.string)
                  000902d5    00000001     --HOLE-- [fill = 0]
                  000902d6    0000004f     device.obj (.const:.string)
                  00090325    00000001     --HOLE-- [fill = 0]
                  00090326    0000004a     driverlib.lib : adc.obj (.const:.string)
                  00090370    0000003c     board.obj (.const:.string)

.TI.ramfunc 
*          0    00086000    0000012d     RUN ADDR = 00008000
                  00086000    0000003f     driverlib.lib : flash.obj (.TI.ramfunc:Flash_initModule)
                  0008603f    0000002d                   : flash.obj (.TI.ramfunc:Flash_setBankPowerMode)
                  0008606c    00000022                   : flash.obj (.TI.ramfunc:Flash_setWaitstates)
                  0008608e    0000001e                   : flash.obj (.TI.ramfunc:Flash_setPumpPowerMode)
                  000860ac    0000001a                   : flash.obj (.TI.ramfunc:Flash_disableCache)
                  000860c6    0000001a                   : flash.obj (.TI.ramfunc:Flash_disablePrefetch)
                  000860e0    00000019                   : flash.obj (.TI.ramfunc:Flash_enableCache)
                  000860f9    00000019                   : flash.obj (.TI.ramfunc:Flash_enablePrefetch)
                  00086112    00000017                   : flash.obj (.TI.ramfunc:Flash_enableECC)
                  00086129    00000004                   : sysctl.obj (.TI.ramfunc)

.text      0    00082000    00001444     
                  00082000    00000167     device.obj (.text:Device_enableAllPeripherals)
                  00082167    00000138     driverlib.lib : sysctl.obj (.text:SysCtl_setClock)
                  0008229f    00000117                   : sysctl.obj (.text:SysCtl_setAuxClock)
                  000823b6    00000110                   : sysctl.obj (.text:SysCtl_isPLLValid)
                  000824c6    000000c9                   : dcc.obj (.text:DCC_verifyClockFrequency)
                  0008258f    00000088     rts2800_fpu64_eabi.lib : fs_div28.asm.obj (.text)
                  00082617    0000007a     driverlib.lib : dcc.obj (.text:DCC_setCounterSeeds)
                  00082691    0000007a                   : sysctl.obj (.text:DCC_setCounterSeeds)
                  0008270b    00000079     adc_ex1_soc_software.obj (.text:main)
                  00082784    00000070     driverlib.lib : adc.obj (.text:ADC_setINLTrim)
                  000827f4    0000006b     device.obj (.text:Device_init)
                  0008285f    00000067     driverlib.lib : sysctl.obj (.text:SysCtl_getAuxClock)
                  000828c6    00000060                   : sysctl.obj (.text:SysCtl_getClock)
                  00082926    00000058                   : adc.obj (.text:ADC_setOffsetTrim)
                  0008297e    00000056     board.obj (.text:ADC_init)
                  000829d4    00000054     driverlib.lib : sysctl.obj (.text:SysCtl_selectOscSource)
                  00082a28    00000052                   : gpio.obj (.text:GPIO_setPadConfig)
                  00082a7a    00000047     board.obj (.text:GPIO_init)
                  00082ac1    00000047     driverlib.lib : sysctl.obj (.text:SysCtl_selectOscSourceAuxPLL)
                  00082b08    00000045     adc_ex1_soc_software.obj (.text:GPIO_writePin)
                  00082b4d    0000003d     driverlib.lib : interrupt.obj (.text:Interrupt_initModule)
                  00082b8a    0000003c     adc_ex1_soc_software.obj (.text:GPIO_togglePin)
                  00082bc6    00000039     board.obj (.text:ADC_setupSOC)
                  00082bff    00000038     driverlib.lib : gpio.obj (.text:GPIO_setMasterCore)
                  00082c37    00000038                   : gpio.obj (.text:GPIO_setQualificationMode)
                  00082c6f    00000037                   : gpio.obj (.text:GPIO_setPinConfig)
                  00082ca6    00000031                   : gpio.obj (.text:GPIO_setDirectionMode)
                  00082cd7    00000031     rts2800_fpu64_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss)
                  00082d08    0000002f     board.obj (.text:ADC_setInterruptSOCTrigger)
                  00082d37    0000002b     rts2800_fpu64_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit)
                  00082d62    0000002a     driverlib.lib : sysctl.obj (.text:SysCtl_pollX1Counter)
                  00082d8c    00000029     rts2800_fpu64_eabi.lib : exit.c.obj (.text)
                  00082db5    00000028     driverlib.lib : adc.obj (.text:ADC_setMode)
                  00082ddd    00000027     board.obj (.text:ADC_setInterruptSource)
                  00082e04    00000025     driverlib.lib : dcc.obj (.text:DCC_enableSingleShotMode)
                  00082e29    00000025                   : sysctl.obj (.text:DCC_enableSingleShotMode)
                  00082e4e    00000024                   : sysctl.obj (.text:SysCtl_selectXTAL)
                  00082e72    00000023     adc_ex1_soc_software.obj (.text:ADC_readResult)
                  00082e95    00000022     board.obj (.text:ADC_disableContinuousMode)
                  00082eb7    00000021     board.obj (.text:ADC_enableInterrupt)
                  00082ed8    00000021     device.obj (.text:Device_initGPIO)
                  00082ef9    0000001f     adc_ex1_soc_software.obj (.text:ADC_isBaseValid)
                  00082f18    0000001f     board.obj (.text:ADC_isBaseValid)
                  00082f37    0000001f     driverlib.lib : adc.obj (.text:ADC_isBaseValid)
                  00082f56    0000001f                   : dcc.obj (.text:DCC_setCounter0ClkSource)
                  00082f75    0000001f                   : sysctl.obj (.text:DCC_setCounter0ClkSource)
                  00082f94    0000001f                   : dcc.obj (.text:DCC_setCounter1ClkSource)
                  00082fb3    0000001f                   : sysctl.obj (.text:DCC_setCounter1ClkSource)
                  00082fd2    0000001e     adc_ex1_soc_software.obj (.text:ADC_getInterruptStatus)
                  00082ff0    0000001e     device.obj (.text:Device_verifyXTAL)
                  0008300e    0000001e     driverlib.lib : interrupt.obj (.text:Interrupt_initVectorTable)
                  0008302c    0000001d     board.obj (.text:ADC_setSOCPriority)
                  00083049    0000001d     driverlib.lib : dcc.obj (.text:DCC_getErrorStatus)
                  00083066    0000001d                   : dcc.obj (.text:DCC_getSingleShotStatus)
                  00083083    0000001d     rts2800_fpu64_eabi.lib : memcpy.c.obj (.text)
                  000830a0    0000001a     driverlib.lib : dcc.obj (.text:DCC_isBaseValid)
                  000830ba    0000001a                   : sysctl.obj (.text:DCC_isBaseValid)
                  000830d4    0000001a                   : sysctl.obj (.text:SysCtl_getLowSpeedClock)
                  000830ee    0000001a                   : sysctl.obj (.text:SysCtl_selectXTALSingleEnded)
                  00083108    00000019     rts2800_fpu64_eabi.lib : boot28.asm.obj (.text)
                  00083121    00000017     board.obj (.text:ADC_setInterruptPulseMode)
                  00083138    00000017     board.obj (.text:ADC_setPrescaler)
                  0008314f    00000017     driverlib.lib : dcc.obj (.text:DCC_disableDoneSignal)
                  00083166    00000017                   : sysctl.obj (.text:DCC_disableDoneSignal)
                  0008317d    00000017                   : dcc.obj (.text:DCC_enableDoneSignal)
                  00083194    00000017     device.obj (.text:SysCtl_enablePeripheral)
                  000831ab    00000017     driverlib.lib : sysctl.obj (.text:SysCtl_enablePeripheral)
                  000831c2    00000016     board.obj (.text:ADC_disableBurstMode)
                  000831d8    00000016     driverlib.lib : dcc.obj (.text:DCC_clearDoneFlag)
                  000831ee    00000016                   : sysctl.obj (.text:DCC_clearDoneFlag)
                  00083204    00000016                   : dcc.obj (.text:DCC_clearErrorFlag)
                  0008321a    00000016                   : sysctl.obj (.text:DCC_clearErrorFlag)
                  00083230    00000016                   : dcc.obj (.text:DCC_disableErrorSignal)
                  00083246    00000016                   : sysctl.obj (.text:DCC_disableErrorSignal)
                  0008325c    00000015     adc_ex1_soc_software.obj (.text:ADC_clearInterruptStatus)
                  00083271    00000015     board.obj (.text:ADC_clearInterruptStatus)
                  00083286    00000015     adc_ex1_soc_software.obj (.text:ADC_forceMultipleSOC)
                  0008329b    00000015     device.obj (.text:GPIO_unlockPortConfig)
                  000832b0    00000014     board.obj (.text:ADC_enableConverter)
                  000832c4    00000014     driverlib.lib : dcc.obj (.text:DCC_disableModule)
                  000832d8    00000014                   : sysctl.obj (.text:DCC_disableModule)
                  000832ec    00000014                   : dcc.obj (.text:DCC_enableErrorSignal)
                  00083300    00000014                   : dcc.obj (.text:DCC_enableModule)
                  00083314    00000014                   : sysctl.obj (.text:DCC_enableModule)
                  00083328    00000014     board.obj (.text:PinMux_init)
                  0008333c    00000013     device.obj (.text:Device_enableUnbondedGPIOPullupsFor176Pin)
                  0008334f    00000011     device.obj (.text:Device_enableUnbondedGPIOPullups)
                  00083360    00000011     device.obj (.text:SysCtl_setCMClk)
                  00083371    00000010     driverlib.lib : flash.obj (.text:Flash_isCtrlBaseValid)
                  00083381    00000010                   : flash.obj (.text:Flash_isECCBaseValid)
                  00083391    0000000e     adc_ex1_soc_software.obj (.text:GPIO_isPinValid)
                  0008339f    0000000e     driverlib.lib : gpio.obj (.text:GPIO_isPinValid)
                  000833ad    0000000e                   : interrupt.obj (.text:Interrupt_defaultHandler)
                  000833bb    0000000d                   : interrupt.obj (.text:Interrupt_disableMaster)
                  000833c8    0000000d     device.obj (.text:SysCtl_setLowSpeedClock)
                  000833d5    0000000d     rts2800_fpu64_eabi.lib : copy_zero_init.c.obj (.text:decompress:ZI:__TI_zero_init_nomemset)
                  000833e2    0000000c     driverlib.lib : sysctl.obj (.text:SysCtl_setPLLSysClk)
                  000833ee    0000000c     rts2800_fpu64_eabi.lib : args_main.c.obj (.text)
                  000833fa    0000000b     driverlib.lib : sysctl.obj (.text:SysCtl_isMCDClockFailureDetected)
                  00083405    00000009     board.obj (.text:Board_init)
                  0008340e    00000009     rts2800_fpu64_eabi.lib : _lock.c.obj (.text)
                  00083417    00000008     device.obj (.text:SysCtl_disableWatchdog)
                  0008341f    00000008     rts2800_fpu64_eabi.lib : copy_decompress_none.c.obj (.text:decompress:none)
                  00083427    00000008     f2838x_codestartbranch.obj (.text)
                  0008342f    00000007     driverlib.lib : sysctl.obj (.text:SysCtl_resetMCD)
                  00083436    00000007     device.obj (.text:__error__)
                  0008343d    00000002     driverlib.lib : interrupt.obj (.text:Interrupt_illegalOperationHandler)
                  0008343f    00000002                   : interrupt.obj (.text:Interrupt_nmiHandler)
                  00083441    00000002     rts2800_fpu64_eabi.lib : pre_init.c.obj (.text)
                  00083443    00000001                            : startup.c.obj (.text)

MODULE SUMMARY

       Module                       code   ro data   rw data
       ------                       ----   -------   -------
    .\
       adc_ex1_soc_software.obj     402    121       1      
    +--+----------------------------+------+---------+---------+
       Total:                       402    121       1      
                                                            
    .\device\
       device.obj                   654    79        0      
       f2838x_codestartbranch.obj   10     0         0      
    +--+----------------------------+------+---------+---------+
       Total:                       664    79        0      
                                                            
    .\syscfg\
       board.obj                    565    60        0      
    +--+----------------------------+------+---------+---------+
       Total:                       565    60        0      
                                                            
    C:/ti/C2000Ware_4_00_00_00/driverlib/f2838x/driverlib/ccs/Debug/driverlib.lib
       sysctl.obj                   1784   151       0      
       dcc.obj                      678    148       0      
       flash.obj                    626    152       0      
       gpio.obj                     312    151       0      
       adc.obj                      271    74        0      
       interrupt.obj                122    0         0      
    +--+----------------------------+------+---------+---------+
       Total:                       3793   676       0      
                                                            
    C:\ti\ccs1110\ccs\tools\compiler\ti-cgt-c2000_21.6.0.LTS\lib\rts2800_fpu64_eabi.lib
       fs_div28.asm.obj             136    0         0      
       copy_decompress_lzss.c.obj   49     0         0      
       exit.c.obj                   41     0         6      
       autoinit.c.obj               43     0         0      
       memcpy.c.obj                 29     0         0      
       boot28.asm.obj               25     0         0      
       _lock.c.obj                  9      0         4      
       copy_zero_init.c.obj         13     0         0      
       args_main.c.obj              12     0         0      
       copy_decompress_none.c.obj   8      0         0      
       pre_init.c.obj               2      0         0      
       startup.c.obj                1      0         0      
    +--+----------------------------+------+---------+---------+
       Total:                       368    0         10     
                                                            
       Stack:                       0      0         1016   
       Linker Generated:            0      27        0      
    +--+----------------------------+------+---------+---------+
       Grand Total:                 5792   963       1027   


LINKER GENERATED COPY TABLES

__TI_cinit_table @ 00088014 records: 2, size/record: 4, table size: 8
	.data: load addr=00088000, load size=00000009 bytes, run addr=0000a800, run size=0000000a bytes, compression=lzss
	.bss: load addr=00088010, load size=00000004 bytes, run addr=0000a80a, run size=00000001 bytes, compression=zero_init


LINKER GENERATED HANDLER TABLE

__TI_handler_table @ 0008800a records: 3, size/record: 2, table size: 6
	index: 0, handler: __TI_zero_init
	index: 1, handler: __TI_decompress_lzss
	index: 2, handler: __TI_decompress_none


GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE

address     data page           name
--------    ----------------    ----
00000400      10 (00000400)     __stack

0000a800     2a0 (0000a800)     __TI_enable_exit_profile_output
0000a802     2a0 (0000a800)     __TI_cleanup_ptr
0000a804     2a0 (0000a800)     __TI_dtors_ptr
0000a806     2a0 (0000a800)     _lock
0000a808     2a0 (0000a800)     _unlock
0000a80a     2a0 (0000a800)     myADC0Result1


GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name 

page  address   name                                     
----  -------   ----                                     
0     0008297e  ADC_init                                 
0     00082784  ADC_setINLTrim                           
0     00082db5  ADC_setMode                              
0     00082926  ADC_setOffsetTrim                        
0     00083405  Board_init                               
0     00082d8c  C$$EXIT                                  
0     000824c6  DCC_verifyClockFrequency                 
0     00082000  Device_enableAllPeripherals              
0     0008334f  Device_enableUnbondedGPIOPullups         
0     0008333c  Device_enableUnbondedGPIOPullupsFor176Pin
0     000827f4  Device_init                              
0     00082ed8  Device_initGPIO                          
0     00082ff0  Device_verifyXTAL                        
0     00008000  Flash_initModule                         
0     00082a7a  GPIO_init                                
0     00082ca6  GPIO_setDirectionMode                    
0     00082bff  GPIO_setMasterCore                       
0     00082a28  GPIO_setPadConfig                        
0     00082c6f  GPIO_setPinConfig                        
0     00082c37  GPIO_setQualificationMode                
0     00082b4d  Interrupt_initModule                     
0     0008300e  Interrupt_initVectorTable                
0     00083328  PinMux_init                              
0     0008612d  RamfuncsLoadEnd                          
abs   0000012d  RamfuncsLoadSize                         
0     00086000  RamfuncsLoadStart                        
0     0000812d  RamfuncsRunEnd                           
abs   0000012d  RamfuncsRunSize                          
0     00008000  RamfuncsRunStart                         
0     00008129  SysCtl_delay                             
0     0008285f  SysCtl_getAuxClock                       
0     000828c6  SysCtl_getClock                          
0     000830d4  SysCtl_getLowSpeedClock                  
0     000823b6  SysCtl_isPLLValid                        
0     000829d4  SysCtl_selectOscSource                   
0     00082ac1  SysCtl_selectOscSourceAuxPLL             
0     00082e4e  SysCtl_selectXTAL                        
0     000830ee  SysCtl_selectXTALSingleEnded             
0     0008229f  SysCtl_setAuxClock                       
0     00082167  SysCtl_setClock                          
0     00088014  __TI_CINIT_Base                          
0     0008801c  __TI_CINIT_Limit                         
0     0008801c  __TI_CINIT_Warm                          
0     0008800a  __TI_Handler_Table_Base                  
0     00088010  __TI_Handler_Table_Limit                 
0     000007f8  __TI_STACK_END                           
abs   000003f8  __TI_STACK_SIZE                          
0     00082d37  __TI_auto_init_nobinit_nopinit           
0     0000a802  __TI_cleanup_ptr                         
0     00082cd7  __TI_decompress_lzss                     
0     0008341f  __TI_decompress_none                     
0     0000a804  __TI_dtors_ptr                           
0     0000a800  __TI_enable_exit_profile_output          
abs   ffffffff  __TI_pprof_out_hndl                      
abs   ffffffff  __TI_prof_data_size                      
abs   ffffffff  __TI_prof_data_start                     
0     000833d5  __TI_zero_init_nomemset                  
0     0008258f  __c28xabi_divf                           
n/a   UNDEFED   __c_args__                               
0     00083436  __error__                                
0     00000400  __stack                                  
0     000833ee  _args_main                               
0     00083108  _c_int00                                 
0     0000a806  _lock                                    
0     00083416  _nop                                     
0     00083412  _register_lock                           
0     0008340e  _register_unlock                         
0     00083443  _system_post_cinit                       
0     00083441  _system_pre_init                         
0     0000a808  _unlock                                  
0     00082d8c  abort                                    
0     00080000  code_start                               
0     00082d8e  exit                                     
0     0008270b  main                                     
0     00083083  memcpy                                   
0     0000a80a  myADC0Result1                            


GLOBAL SYMBOLS: SORTED BY Symbol Address 

page  address   name                                     
----  -------   ----                                     
0     00000400  __stack                                  
0     000007f8  __TI_STACK_END                           
0     00008000  Flash_initModule                         
0     00008000  RamfuncsRunStart                         
0     00008129  SysCtl_delay                             
0     0000812d  RamfuncsRunEnd                           
0     0000a800  __TI_enable_exit_profile_output          
0     0000a802  __TI_cleanup_ptr                         
0     0000a804  __TI_dtors_ptr                           
0     0000a806  _lock                                    
0     0000a808  _unlock                                  
0     0000a80a  myADC0Result1                            
0     00080000  code_start                               
0     00082000  Device_enableAllPeripherals              
0     00082167  SysCtl_setClock                          
0     0008229f  SysCtl_setAuxClock                       
0     000823b6  SysCtl_isPLLValid                        
0     000824c6  DCC_verifyClockFrequency                 
0     0008258f  __c28xabi_divf                           
0     0008270b  main                                     
0     00082784  ADC_setINLTrim                           
0     000827f4  Device_init                              
0     0008285f  SysCtl_getAuxClock                       
0     000828c6  SysCtl_getClock                          
0     00082926  ADC_setOffsetTrim                        
0     0008297e  ADC_init                                 
0     000829d4  SysCtl_selectOscSource                   
0     00082a28  GPIO_setPadConfig                        
0     00082a7a  GPIO_init                                
0     00082ac1  SysCtl_selectOscSourceAuxPLL             
0     00082b4d  Interrupt_initModule                     
0     00082bff  GPIO_setMasterCore                       
0     00082c37  GPIO_setQualificationMode                
0     00082c6f  GPIO_setPinConfig                        
0     00082ca6  GPIO_setDirectionMode                    
0     00082cd7  __TI_decompress_lzss                     
0     00082d37  __TI_auto_init_nobinit_nopinit           
0     00082d8c  C$$EXIT                                  
0     00082d8c  abort                                    
0     00082d8e  exit                                     
0     00082db5  ADC_setMode                              
0     00082e4e  SysCtl_selectXTAL                        
0     00082ed8  Device_initGPIO                          
0     00082ff0  Device_verifyXTAL                        
0     0008300e  Interrupt_initVectorTable                
0     00083083  memcpy                                   
0     000830d4  SysCtl_getLowSpeedClock                  
0     000830ee  SysCtl_selectXTALSingleEnded             
0     00083108  _c_int00                                 
0     00083328  PinMux_init                              
0     0008333c  Device_enableUnbondedGPIOPullupsFor176Pin
0     0008334f  Device_enableUnbondedGPIOPullups         
0     000833d5  __TI_zero_init_nomemset                  
0     000833ee  _args_main                               
0     00083405  Board_init                               
0     0008340e  _register_unlock                         
0     00083412  _register_lock                           
0     00083416  _nop                                     
0     0008341f  __TI_decompress_none                     
0     00083436  __error__                                
0     00083441  _system_pre_init                         
0     00083443  _system_post_cinit                       
0     00086000  RamfuncsLoadStart                        
0     0008612d  RamfuncsLoadEnd                          
0     0008800a  __TI_Handler_Table_Base                  
0     00088010  __TI_Handler_Table_Limit                 
0     00088014  __TI_CINIT_Base                          
0     0008801c  __TI_CINIT_Limit                         
0     0008801c  __TI_CINIT_Warm                          
abs   0000012d  RamfuncsLoadSize                         
abs   0000012d  RamfuncsRunSize                          
abs   000003f8  __TI_STACK_SIZE                          
abs   ffffffff  __TI_pprof_out_hndl                      
abs   ffffffff  __TI_prof_data_size                      
abs   ffffffff  __TI_prof_data_start                     
n/a   UNDEFED   __c_args__                               

[76 symbols]

From what I see it looks OK codestart origin is 00080000:

Hi,

Th codestart looks correct. This is important for standalone execution.

Can you check if you have watchdog disabled during codestart? WD_DSIABLE macro should be 1. Watchdog can cause device reset

WD_DISABLE  .set  1    ;set to 1 to disable WD, else set to 0

    .ref _c_int00
    .global code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"
    .retain

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB _c_int00         ;Branch to start of boot._asm in RTS library
    .endif

;end codestart section

Regards,

Veena

Hi Veena,

Here is my f2838x_codestartbranch.asm

;//###########################################################################
;//
;// FILE:  f2838x_codestartbranch.asm
;//
;// TITLE: Branch for redirecting code execution after boot.
;//
;// For these examples, code_start is the first code that is executed after
;// exiting the boot ROM code.
;//
;// The codestart section in the linker cmd file is used to physically place
;// this code at the correct memory location.  This section should be placed
;// at the location the BOOT ROM will re-direct the code to.  For example,
;// for boot to FLASH this code will be located at 0x3f7ff6.
;//
;// In addition, the example F2838x projects are setup such that the codegen
;// entry point is also set to the code_start label.  This is done by linker
;// option -e in the project build options.  When the debugger loads the code,
;// it will automatically set the PC to the "entry point" address indicated by
;// the -e linker option.  In this case the debugger is simply assigning the PC,
;// it is not the same as a full reset of the device.
;//
;// The compiler may warn that the entry point for the project is other then
;//  _c_init00.  _c_init00 is the C environment setup and is run before
;// main() is entered. The code_start code will re-direct the execution
;// to _c_init00 and thus there is no worry and this warning can be ignored.
;//
;//###########################################################################
;//
;//
;// $Copyright: $
;//###########################################################################

***********************************************************************

WD_DISABLE  .set  1    ;set to 1 to disable WD, else set to 0

    .ref _c_int00
    .global code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"
    .retain

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB _c_int00         ;Branch to start of boot._asm in RTS library
    .endif

;end codestart section

***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
    .if WD_DISABLE == 1

    .text
wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    LB _c_int00         ;Branch to start of boot._asm in RTS library

    .endif

;end wd_disable

    .end

;//
;// End of file.
;//

as you see the WD_DSIABLE is 1

I probed the signals 3V3, 1V2, XRS and 25MhzClock and GPIO72 and 82:

From what I see the XRSn goes high too soon when the uC does not boot in flash.
When it works the XRSN takes around 2ms to go high.

I mounted on my board a reset switch:

And when I press the switch the uC is now booting to flash , same if I keep the switch pressed, power the board and release the switch it goes to flash.

The supervisors 3V3 and 1V2 look like they are doing there job...

Is there anything inside the uC that should keep the XRSn signal low during the power  up?

Is it possible to assert a reset later after the POR or add a delay after the tw(RSL1) = 100us(Typ)?

Hi,

I will forward this query to JTAG/Board Schematic experts.

Regards,

Veena

Thank you Veena,

In the meantime do you know if there is a easy fix I can do in the software like add some delay and do a software reset after a Power On Reset?

Alexis Maslyczyk said:

From what I see the XRSn goes high too soon when the uC does not boot in flash.

From what I see the problem is not with the XRSn going too soon or too late, the supervisors are doing its job perfectly, and because the 3V3 rail is below 3.17V (datasheet threshold) XRSn must be held low.
The longer reset is caused by slower 3V3 ramp.
The question is: why the 3V3 ramp slows down during power up?

Regards,
Andy

Hi Andy, you are right, it is hard to tell  why when it does not boot in flash the 3v3 goes straight to 3.3V VS when it does boot in flash, there is a slow ramp. Maybe it is because it is booting to flash and initialize all the GPIO and stuff?

I have not a lot of thing on the 3V3, one IMU, EtherCAT stuff, one temp sensor and one ADC reference.

I did change some component values, added more capa next to the supervisors and bigger filter on XRES. 

Now it is always booting in flash, but if I toggle the power supply I have to wait 5sec before turning back on otherwise it does not boot. It is really strange.

1. Turn on 12V Vin
2. uC boot in flash
3. Toggle the power supply (Off,On)
4. uC does not boot in flash
5. Turn off 12V Vin
6. Wait 5sec
7. Turn on 12V Vin
8. uC boot in flash

The behavior is really consistent. It is like somehow, somewhere, something stay high and prevent me to go in flash.

I can share the schematics if you are interested to take a look at it.

PCB_F2838_Node_TI.pdf

Alexis, 

Can you include a scope capture of VDD, VDDIO, XRSn in the two conditions described above. one with a 5 second delay and one without?

The MCU can and does hold its XRS pin low for an amount of time during boot, but likely your supervisor is probably forcing low as well. 

Thanks,
Cody 

Hi Cody,

When I toggle the power supply and it does not boot in flash:

When I wait 5sec and it does boot in flash:

As Andy was saying, the two supervisors do their job, the 3V3 slope is different and make the XRSn low longer when it boot vs when it does not, I am not sure if it is a cause or the reason why it boots to flash .

I would pay more attention to the power supply. The 3V3 really shouldn't behave like this. Can you also check the +5V supply? Maybe there is something wrong?

Andy

Ah, I now see the slope change in your earlier post, it is much more clear in these photos.

I absolutely agree with Andy, we need to know why the 3.3V rail is behaving this way, the 5V rail may give some clues.

Regards,
Cody

Thank you guys for pointing me to the right direction. 

I will double check that, having two buck converters chained was not the best idea. My rational behind that was to use the first one to get a big range of Vin 6-60V and the other one to get the 3V3 and 1V2 is copy/paste of the control card to avoid any design mistake 

I will try to use the PG (power good) pin to start the the next converter.