Hi experts,
My customer is currently considering the F2837xS and we are discussing the need for a reset IC.
Taking into account design errors and margins, we believe that VDD is outside the recommended voltage range of 1.01 to 1.14V and may fall into the area where POR is not applied. Is this a problem if the time is short enough? If so, could you give me a quantitative upper limit?
I have the following understanding about the necessity of the reset IC. Refer to:e2e.ti.com/.../3538747
If VDDIO/VDD reaches 2.3V and 1.0V and falls within the Vmin of the device after 100us, the reset can be held properly. (The trigger point is about 2.3V for the VDDIO rail and about 1.0V for the 1.2V rail.) If not, it is recommended to use an external power supply monitoring IC (reset IC) or other device that holds XRSn until the power supply rail reaches Vmin.
For the above, I think you are assuming the rise of the power supply voltage at startup. In this time case, we are more concerned about the instantaneous voltage drop due to sudden load changes such as Flash Erase of the MCU after the power supply rises. When the maximum load described in the datasheet was applied in steps, a voltage drop of several 10mV was observed. I would appreciate your opinion on the necessity of a reset IC for this case.
Best regards,
O.H