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Dear TI team,
We have our custom board using TMS320F28384D , our application is to write value in flash sector (Bzero_Sector6_start ) of regular interval 10secs..its working fine in running state,
while(program_start==1)
{
if(Write_Sec>=10){
spindle_parameter();
Flash_claimPumpSemaphore(FLASH_CPU1_WRAPPER);
EEPROM_Erase(Bzero_Sector6_start);
EEPROM_ProgramSingleByte(spindle1_parameter,12,Bzero_Sector6_start);
Flash_releasePumpSemaphore();
Write_Sec=0;}
}
but while I connect debugger in debug mode , we are facing a issue that erase sector function fails and processor gets hang( estop) in EEPROM_Erase(); function
Most case, while in debug mode works fine for 1 to 2 minute ..after that program get strucks in erase function.
processor struck in "oReturnCheck = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,(uint32*)Bzero_SectorB_start2);"" please find function below.
//############################ EEPROM_ERASE_START- Sector C ######################################################################################
void EEPROM_Erase(uint32 ERASESECTOR)
{
DINT;
EALLOW;
uint32 Bzero_SectorB_start2;
Bzero_SectorB_start2= ERASESECTOR;
oReturnCheck = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,(uint32*)Bzero_SectorB_start2);
//
// Wait until FSM is done with erase sector operation
//
while (Fapi_checkFsmForReady() != Fapi_Status_FsmReady){
}
// Read FMSTAT register contents to know the status of FSM after
// erase command to see if there are any erase operation related errors
//
oFlashStatus = Fapi_getFsmStatus();
if(oFlashStatus != 0)
{
//
// Check Flash API documentation for FMSTAT and debug accordingly
// Fapi_getFsmStatus() function gives the FMSTAT register contents.
// Check to see if any of the EV bit, ESUSP bit, CSTAT bit or
// VOLTSTAT bit is set (Refer to API documentation for more details).
//
__asm(" ESTOP0");
}
//
// Verify that SectorL is erased. The Erase step itself does a
// verify as it goes. This verify is a 2nd verification that can be done.
//
oReturnCheck = Fapi_doBlankCheck((uint32 *)Bzero_SectorB_start2,
Bzero_64KSector_u32length,
&oFlashStatusWord);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
// If Erase command fails, use Fapi_getFsmStatus() function to get the
// FMSTAT register contents to see if any of the EV bit, ESUSP bit,
// CSTAT bit or VOLTSTAT bit is set (Refer to API documentation for
// more details)
//
Example_Error(oReturnCheck);
}
c1=4;
EDIS;
EINT;
}
kindly, help us to solve this issue and provide a solution
Thanks & Regards,
Ajay S
Hi Ajay,
I will review this and get back to you in a day or two.
Thanks and regards,
Vamsi
Ajay,
Are flash API and EEPROM_Erase() mapped to execute from RAM or not? They should be mapped to RAM - please confirm.
Also, I noticed in your code snippet that the erase function is hardcoded to always erase sectorB irrespective of which address you pass in - Is that intentional?
Thanks and regards,
Vamsi
Vamsi,
yes, we have executing "EEPROM_ERASE" in ram function as mentioned below . As our application need to update value in every 10secs ..so we are hard-coding erase sector purposely.. kindly provide us better solution for hard-coding.
main.c:
#pragma CODE_SECTION(EEPROM_Erase,"TI.ramfunc");
#pragma CODE_SECTION(EEPROM_Write,"TI.ramfunc");
flash linker command file:
GROUP
{
.TI.ramfunc
{ -l F2838x_C28x_FlashAPI.lib}
} LOAD = FLASH3,
RUN = RAMLS03,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
Thanks®ards,
Ajay S
Ajay,
You are executing both the flash API and EEPROM_Erase from RAM - which is good.
When you say it halts at ESTOP-> Do you mean the ESTOP in the code snippet that you showed near the oFlashStatus check? OR is it ending up in a BootROM address? If it is a BootROM address, can you check if it falls in to any of the below ranges?
Regarding hard-coding: Sorry, I missed reading "Bzero_SectorB_start2= ERASESECTOR;" in your code. I now see that it is not hard-coded and is actually taking the parameter passed in for sector erase.
Please note: I am out of office up to March 3rd. Please expect delay in my response.
Thanks and regards,
Vamsi
Dear Vamsi,
Thanks for the response. As mentioned ,when the processor hangs in ERASE SECTOR Function.
step1:
initial code hangs in " oReturnCheck = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,
(uint32*)Bzero_SectorB_start2);"
step2:
When forces the code execution to stepover.
step3:
when try to resume the code execution "RESUME"
NOTE: "CPU2 GETTING HELD IN RESET"
C28xx_CPU2: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU2: Trouble Reading Register PC: (Error -1137 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register RPC: (Error -1137 @ 0x13) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register ST1: (Error -1137 @ 0x6) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register PC: (Error -1137 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register RPC: (Error -1137 @ 0x13) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register ST1: (Error -1137 @ 0x6) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register PC: (Error -1137 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register RPC: (Error -1137 @ 0x13) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register ST1: (Error -1137 @ 0x6) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
C28xx_CPU2: Trouble Reading Register PC: (Error -1137 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 9.2.0.00002)
"Is it ending up in a Bootrom address?"
Where we have to check the Bootrom address ,not yet checked out ? kindly help us and provide us solution.
As we have checked out with FAPI Technical reference manual,
our application need to erase and write 24bytes every 10secs once for 365days . Then also after from power failure we will retrieve the values. kindly suggest us lifetime of f28384d or need to go with external "SRAM".
Thanks& Regards,
Ajay S
Hi Ajay,
1) Address 0x3FE96F in your CCS debug window snapshot is the ITRAP ISR in BootROM space. Meaning, CPU executed an illegal opcode. Please make sure the flash API code and the EEPROM_Erase() are still intact in RAM when you notice this issue.
2) Regarding your flash erase usage: How many times is the sector erased in your application totally? It is not clear from your message. Below datasheet flash parameter spec table shows that a sector can be erased for a max of 20k times.
Thanks and regards,
Vamsi
Dear TI Team,
Hope u were back to work,
2. We are erasing sector every 10 secs once - for a minute 6 times for a whole 365 days, this means if we erase and write likewise . How long will be the lifecycle of sector? and How long will be life of processor ?
1.We are executing flash code with "ram function",Herewith attached linker file for your reference.
How we can check bootrom space and illegal code execution? Help us to solve the illegal code executed and resolve this error.
MEMORY { /* BEGIN is used for the "boot to Flash" bootloader mode */ BEGIN : origin = 0x080000, length = 0x000002 BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x0001B1, length = 0x00024F RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ // RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMD0 : origin = 0x00C000, length = 0x000800 RAMD1 : origin = 0x00C800, length = 0x000800 RAMLS03 : origin = 0x008000, length = 0x002000 RAMLS4 : origin = 0x00A000, length = 0x000800 RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 RAMLS7 : origin = 0x00B800, length = 0x000800 RAMGS0 : origin = 0x00D000, length = 0x001000 RAMGS1 : origin = 0x00E000, length = 0x001000 RAMGS2 : origin = 0x00F000, length = 0x001000 RAMGS3 : origin = 0x010000, length = 0x001000 RAMGS4 : origin = 0x011000, length = 0x001000 RAMGS5 : origin = 0x012000, length = 0x001000 RAMGS6 : origin = 0x013000, length = 0x001000 RAMGS7 : origin = 0x014000, length = 0x001000 RAMGS8 : origin = 0x015000, length = 0x001000 RAMGS9 : origin = 0x016000, length = 0x001000 RAMGS10 : origin = 0x017000, length = 0x001000 RAMGS11 : origin = 0x018000, length = 0x001000 RAMGS12 : origin = 0x019000, length = 0x001000 RAMGS13 : origin = 0x01A000, length = 0x001000 RAMGS14 : origin = 0x01B000, length = 0x001000 RAMGS15 : origin = 0x01C000, length = 0x000FF8 // RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ /* Flash sectors */ FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */ FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */ FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */ FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */ FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */ FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */ FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ // FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800 CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800 CPUTOCMRAM : origin = 0x039000, length = 0x000800 CMTOCPURAM : origin = 0x038000, length = 0x000800 CANA_MSG_RAM : origin = 0x049000, length = 0x000800 CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 RESET : origin = 0x3FFFC0, length = 0x000002 } SECTIONS { codestart : > BEGIN, ALIGN(8) .text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(8) .cinit : > FLASH1| FLASH2 | FLASH3| FLASH4 , ALIGN(8) .switch : > FLASH1, ALIGN(8) .reset : > RESET, TYPE = DSECT /* not used, */ .stack : > RAMM1 .init_array : > FLASH1, ALIGN(8) .bss : > RAMLS5 .bss:output : > RAMLS4 .bss:cio : > RAMLS5 .data : > RAMLS5|RAMLS6|RAMLS7 .sysmem : > RAMLS5 /* Initalized sections go in Flash */ .const : > FLASH5, ALIGN(8) ramgs0 : > RAMGS0, type=NOINIT ramgs1 : > RAMGS1, type=NOINIT MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT DataBufferSection : > RAMM0, ALIGN(8) GROUP { .TI.ramfunc { -l F2838x_C28x_FlashAPI.lib} } LOAD = FLASH3, RUN = RAMLS03, LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd), RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd), ALIGN(8) } /* //=========================================================================== // End of file. //=========================================================================== */
asm file:
......... ... 00085d7d: 761F02C4 MOVW DP, #0x2c4 00085d7f: E2030008 MOV32 @0x8, R0H 00085d81: 761F02C3 MOVW DP, #0x2c3 00085d83: 0E24 MOVU ACC, @0x24 00085d84: BDA90F12 MOV32 R0H, @ACC 00085d86: E8020049 MOVIZ R1, #0x4009 00085d88: E808F5C1 MOVXI R1H, #0x1eb8 00085d8a: 761F02C5 MOVW DP, #0x2c5 00085d8c: E9028F59 MOVIX R1L, #0x51eb 00085d8e: E6870000 UI32TOF64 R0, R0H 00085d90: E90C28F9 MOVXI R1L, #0x851f 00085d92: E7800040 MPYF64 R0, R0, R1 00085d94: E285010A UI32TOF64 R1, @0xa 00085d96: 7700 NOP 00085d97: E7800008 MPYF64 R0, R1, R0 00085d99: E801FA81 MOVIZ R1, #0x3f50 00085d9b: E80B1269 MOVXI R1H, #0x624d 00085d9d: E9069789 MOVIX R1L, #0xd2f1 00085d9f: E90D4FE1 MOVXI R1L, #0xa9fc 00085da1: E7800008 MPYF64 R0, R1, R0 00085da3: 7700 NOP 00085da4: 7700 NOP 00085da5: E6860000 F64TOUI32 R0H, R0 00085da7: 761F02C4 MOVW DP, #0x2c4 00085da9: E2030016 MOV32 @0x16, R0H 00085dab: 764852EE LCR Spindle1_Start_Stop 00085dad: 764854A8 LCR Spindle2_Start_Stop 00085daf: 76485662 LCR Spindle3_Start_Stop 00085db1: 76485131 LCR Spindle4_Start_Stop 00085db3: 76487DC9 LCR Spindle1_Yarn_Sensor 00085db5: 761F02B3 MOVW DP, #0x2b3 00085db7: 0624 MOVL ACC, @0x24 00085db8: 761F02B3 MOVW DP, #0x2b3 00085dba: 0F2C CMPL ACC, @0x2c 00085dbb: 6605 SB $C$L56, HI 00085dbc: 761F02C1 MOVW DP, #0x2c1 00085dbe: 56BF0121 MOVB @0x21, #0x01, UNC $C$L56: 00085dc0: 76487E37 LCR Spindle2_Yarn_Sensor 00085dc2: 761F02B3 MOVW DP, #0x2b3 00085dc4: 0626 MOVL ACC, @0x26 00085dc5: 761F02B3 MOVW DP, #0x2b3 00085dc7: 0F32 CMPL ACC, @0x32 00085dc8: 6605 SB $C$L57, HI 00085dc9: 761F02C1 MOVW DP, #0x2c1 00085dcb: 56BF0127 MOVB @0x27, #0x01, UNC $C$L57: 00085dcd: 76487EA5 LCR Spindle3_Yarn_Sensor 00085dcf: 761F02B3 MOVW DP, #0x2b3 00085dd1: 0628 MOVL ACC, @0x28 00085dd2: 761F02B3 MOVW DP, #0x2b3 00085dd4: 0F38 CMPL ACC, @0x38 00085dd5: 6605 SB $C$L58, HI 00085dd6: 761F02C1 MOVW DP, #0x2c1 00085dd8: 56BF012D MOVB @0x2d, #0x01, UNC $C$L58: 00085dda: 76487F13 LCR Spindle4_Yarn_Sensor 00085ddc: 761F02B3 MOVW DP, #0x2b3 00085dde: 062A MOVL ACC, @0x2a 00085ddf: 761F02B3 MOVW DP, #0x2b3 00085de1: 0F3E CMPL ACC, @0x3e 00085de2: 6605 SB $C$L59, HI 00085de3: 761F02C1 MOVW DP, #0x2c1 00085de5: 56BF0133 MOVB @0x33, #0x01, UNC $C$L59: 00085de7: 7648581C LCR pulsefail 00085de9: 76489841 LCR spindle1_Set 00085deb: 764898F5 LCR spindle2_Set 00085ded: 764898FF LCR spindle3_Set 00085def: 76489909 LCR spindle4_Set 00085df1: 764849E0 LCR spindlesec_address 00085df3: 9A01 MOVB AL, #0x1 00085df4: 76489983 LCR Interrupt_clearACKGroup 00085df6: E2AF03BE MOV32 R3H, *--SP, UNCF 00085df8: E2AF02BE MOV32 R2H, *--SP, UNCF 00085dfa: E2AF01BE MOV32 R1H, *--SP, UNCF 00085dfc: E29F01BE MOV32 R1L, *--SP, UNCF 00085dfe: E2AF00BE MOV32 R0H, *--SP, UNCF 00085e00: E29F00BE MOV32 R0L, *--SP, UNCF 00085e02: E28000BE MOV32 STF, *--SP 00085e04: C5BE MOVL XAR7, *--SP 00085e05: C4BE MOVL XAR6, *--SP 00085e06: 83BE MOVL XAR5, *--SP 00085e07: 8ABE MOVL XAR4, *--SP 00085e08: 87BE MOVL XT, *--SP 00085e09: 0003 POP AR1H:AR0H 00085e0a: 3B30 SETC INTM|DBGM 00085e0b: FFF1 POP RB 00085e0c: 7617 NASP 00085e0d: 7602 IRET main(): 00085e0e: FE02 ADDB SP, #2 00085e0f: 7648764D LCR Start_Init 00085e11: 761F02C1 MOVW DP, #0x2c1 00085e13: 2B1E MOV @0x1e, #0 00085e14: 921E MOV AL, @0x1e 00085e15: 5202 CMPB AL, #0x2 00085e16: 6704 SB $C$L57, HIS $C$L56: 00085e17: 921E MOV AL, @0x1e 00085e18: 5202 CMPB AL, #0x2 00085e19: 68FE SB $C$L56, LO $C$L57: 00085e1a: 2B1E MOV @0x1e, #0 00085e1b: 76488980 LCR Sci_Communication_Conf1 00085e1d: 76489520 LCR RS485enable1 00085e1f: 764884BF LCR initSCIAFIFO $C$L58: 00085e21: 761F02D5 MOVW DP, #0x2d5 00085e23: 9202 MOV AL, @0x2 00085e24: 604A SB $C$L63, NEQ $C$L59: 00085e25: 5200 CMPB AL, #0x0 00085e26: 6013 SB $C$L60, NEQ 00085e27: 761F02B3 MOVW DP, #0x2b3 00085e29: 9201 MOV AL, @0x1 00085e2a: 600F SB $C$L60, NEQ 00085e2b: 761F02B3 MOVW DP, #0x2b3 00085e2d: 9207 MOV AL, @0x7 00085e2e: 600B SB $C$L60, NEQ 00085e2f: 761F02B3 MOVW DP, #0x2b3 00085e31: 920D MOV AL, @0xd 00085e32: 6007 SB $C$L60, NEQ 00085e33: 761F02B3 MOVW DP, #0x2b3 00085e35: 9213 MOV AL, @0x13 00085e36: 6003 SB $C$L60, NEQ 00085e37: 76488137 LCR initblink $C$L60: 00085e39: 761F02B3 MOVW DP, #0x2b3 00085e3b: 9201 MOV AL, @0x1 00085e3c: 5201 CMPB AL, #0x1 00085e3d: 6124 SB $C$L61, EQ 00085e3e: 761F02B3 MOVW DP, #0x2b3 00085e40: 9207 MOV AL, @0x7 00085e41: 5201 CMPB AL, #0x1 00085e42: 611F SB $C$L61, EQ 00085e43: 761F02B3 MOVW DP, #0x2b3 00085e45: 920D MOV AL, @0xd 00085e46: 5201 CMPB AL, #0x1 00085e47: 611A SB $C$L61, EQ 00085e48: 761F02B3 MOVW DP, #0x2b3 00085e4a: 9213 MOV AL, @0x13 00085e4b: 5201 CMPB AL, #0x1 00085e4c: 6115 SB $C$L61, EQ 00085e4d: 761F02C0 MOVW DP, #0x2c0 00085e4f: 9230 MOV AL, @0x30 00085e50: 5201 CMPB AL, #0x1 00085e51: 6110 SB $C$L61, EQ 00085e52: 761F02C0 MOVW DP, #0x2c0 00085e54: 923B MOV AL, @0x3b 00085e55: 5201 CMPB AL, #0x1 00085e56: 610B SB $C$L61, EQ 00085e57: 761F02C1 MOVW DP, #0x2c1 00085e59: 9206 MOV AL, @0x6 00085e5a: 5201 CMPB AL, #0x1 00085e5b: 6106 SB $C$L61, EQ 00085e5c: 761F02C1 MOVW DP, #0x2c1 00085e5e: 9211 MOV AL, @0x11 00085e5f: 5201 CMPB AL, #0x1 00085e60: 600A SB $C$L62, NEQ $C$L61: 00085e61: 761F02D5 MOVW DP, #0x2d5 00085e63: 56BF0102 MOVB @0x2, #0x01, UNC 00085e65: 0201 MOVB ACC, #1 00085e66: 1E42 MOVL *-SP[2], ACC 00085e67: 0238 MOVB ACC, #56 00085e68: 76488B56 LCR GPIO_writePin $C$L62: 00085e6a: 761F02D5 MOVW DP, #0x2d5 00085e6c: 9202 MOV AL, @0x2 00085e6d: 61B8 SB $C$L59, EQ $C$L63: 00085e6e: 5201 CMPB AL, #0x1 00085e6f: 60B2 SB $C$L58, NEQ $C$L64: 00085e70: 761F02D5 MOVW DP, #0x2d5 00085e72: 0608 MOVL ACC, @0x8 00085e73: 611B SB $C$L65, EQ 00085e74: 7648819A LCR spindle_parameter 00085e76: 761F02C3 MOVW DP, #0x2c3 00085e78: 062A MOVL ACC, @0x2a 00085e79: 761F02C3 MOVW DP, #0x2c3 00085e7b: 1E28 MOVL @0x28, ACC 00085e7c: 761F02C3 MOVW DP, #0x2c3 00085e7e: 0638 MOVL ACC, @0x38 00085e7f: 761F02C3 MOVW DP, #0x2c3 00085e81: 1E36 MOVL @0x36, ACC 00085e82: 761F02C4 MOVW DP, #0x2c4 00085e84: 0606 MOVL ACC, @0x6 00085e85: 761F02C4 MOVW DP, #0x2c4 00085e87: 1E04 MOVL @0x4, ACC 00085e88: 761F02C4 MOVW DP, #0x2c4 00085e8a: 0614 MOVL ACC, @0x14 00085e8b: 761F02C4 MOVW DP, #0x2c4 00085e8d: 1E12 MOVL @0x12, ACC $C$L65: 00085e8e: 761F02D4 MOVW DP, #0x2d4 00085e90: 923C MOV AL, @0x3c 00085e91: 612E SB $C$L68, EQ 00085e92: 761F02B3 MOVW DP, #0x2b3 00085e94: 9201 MOV AL, @0x1 00085e95: 5201 CMPB AL, #0x1 00085e96: 600F SB $C$L66, NEQ 00085e97: 761F02C3 MOVW DP, #0x2c3 00085e99: 0628 MOVL ACC, @0x28 00085e9a: 761F02C5 MOVW DP, #0x2c5 00085e9c: 0F22 CMPL ACC, @0x22 00085e9d: 6608 SB $C$L66, HI 00085e9e: 76487244 LCR Run_spindle1 00085ea0: 761F02D1 MOVW DP, #0x2d1 00085ea2: 2823028A MOV @0x23, #0x028a 00085ea4: 6F1B SB $C$L68, UNC $C$L66: 00085ea5: 761F02B3 MOVW DP, #0x2b3 00085ea7: 9201 MOV AL, @0x1 00085ea8: 6017 SB $C$L68, NEQ 00085ea9: 761F02D4 MOVW DP, #0x2d4 00085eab: 9220 MOV AL, @0x20 00085eac: 5201 CMPB AL, #0x1 00085ead: 6004 SB $C$L67, NEQ 00085eae: 9A76 MOVB AL, #0x76 00085eaf: 76489650 LCR blinky $C$L67: 00085eb1: 7648994E LCR preTransmission 00085eb3: 8F404B00 MOVL XAR5, #0x004b00 00085eb5: D402 MOVB XAR4, #0x2 00085eb6: A0A9 MOVL @ACC, XAR5 00085eb7: 76489869 LCR ModbusMaster_begin 00085eb9: 28A90C1B MOV @AL, #0x0c1b 00085ebb: 28A801F4 MOV @AH, #0x01f4 00085ebd: 76489767 LCR ModbusMaster_writeSingleRegister $C$L68: 00085ebf: 761F02D4 MOVW DP, #0x2d4 00085ec1: 923D MOV AL, @0x3d 00085ec2: 612E SB $C$L71, EQ 00085ec3: 761F02B3 MOVW DP, #0x2b3 00085ec5: 9207 MOV AL, @0x7 00085ec6: 5201 CMPB AL, #0x1 00085ec7: 600F SB $C$L69, NEQ 00085ec8: 761F02C3 MOVW DP, #0x2c3 00085eca: 0636 MOVL ACC, @0x36 00085ecb: 761F02C5 MOVW DP, #0x2c5 00085ecd: 0F32 CMPL ACC, @0x32 00085ece: 6608 SB $C$L69, HI 00085ecf: 76487314 LCR Run_spindle2 00085ed1: 761F02D1 MOVW DP, #0x2d1 00085ed3: 2823028B MOV @0x23, #0x028b 00085ed5: 6F1B SB $C$L71, UNC $C$L69: 00085ed6: 761F02B3 MOVW DP, #0x2b3 00085ed8: 9207 MOV AL, @0x7 00085ed9: 6017 SB $C$L71, NEQ 00085eda: 761F02D4 MOVW DP, #0x2d4 00085edc: 9221 MOV AL, @0x21 00085edd: 5201 CMPB AL, #0x1 00085ede: 6004 SB $C$L70, NEQ 00085edf: 9A78 MOVB AL, #0x78 00085ee0: 76489650 LCR blinky $C$L70: 00085ee2: 7648994E LCR preTransmission 00085ee4: 8F404B00 MOVL XAR5, #0x004b00 00085ee6: D401 MOVB XAR4, #0x1 00085ee7: A0A9 MOVL @ACC, XAR5 00085ee8: 76489869 LCR ModbusMaster_begin 00085eea: 28A90C1B MOV @AL, #0x0c1b 00085eec: 28A801F4 MOV @AH, #0x01f4 00085eee: 76489767 LCR ModbusMaster_writeSingleRegister $C$L71: 00085ef0: 761F02D4 MOVW DP, #0x2d4 00085ef2: 923E MOV AL, @0x3e 00085ef3: 612E SB $C$L74, EQ 00085ef4: 761F02B3 MOVW DP, #0x2b3 00085ef6: 920D MOV AL, @0xd 00085ef7: 5201 CMPB AL, #0x1 00085ef8: 600F SB $C$L72, NEQ 00085ef9: 761F02C4 MOVW DP, #0x2c4 00085efb: 0604 MOVL ACC, @0x4 00085efc: 761F02C6 MOVW DP, #0x2c6 00085efe: 0F02 CMPL ACC, @0x2 00085eff: 6608 SB $C$L72, HI 00085f00: 764873E4 LCR Run_spindle3 00085f02: 761F02D1 MOVW DP, #0x2d1 00085f04: 2823028C MOV @0x23, #0x028c 00085f06: 6F1B SB $C$L74, UNC $C$L72: 00085f07: 761F02B3 MOVW DP, #0x2b3 00085f09: 920D MOV AL, @0xd 00085f0a: 6017 SB $C$L74, NEQ 00085f0b: 761F02D4 MOVW DP, #0x2d4 00085f0d: 9222 MOV AL, @0x22 00085f0e: 5201 CMPB AL, #0x1 00085f0f: 6004 SB $C$L73, NEQ 00085f10: 9A7A MOVB AL, #0x7a 00085f11: 76489650 LCR blinky $C$L73: 00085f13: 7648994E LCR preTransmission 00085f15: 8F404B00 MOVL XAR5, #0x004b00 00085f17: D403 MOVB XAR4, #0x3 00085f18: A0A9 MOVL @ACC, XAR5 00085f19: 76489869 LCR ModbusMaster_begin 00085f1b: 28A90C1B MOV @AL, #0x0c1b 00085f1d: 28A801F4 MOV @AH, #0x01f4 00085f1f: 76489767 LCR ModbusMaster_writeSingleRegister $C$L74: 00085f21: 761F02D4 MOVW DP, #0x2d4 00085f23: 923F MOV AL, @0x3f 00085f24: 612E SB $C$L77, EQ 00085f25: 761F02B3 MOVW DP, #0x2b3 00085f27: 9213 MOV AL, @0x13 00085f28: 5201 CMPB AL, #0x1 00085f29: 600F SB $C$L75, NEQ 00085f2a: 761F02C4 MOVW DP, #0x2c4 00085f2c: 0612 MOVL ACC, @0x12 00085f2d: 761F02C6 MOVW DP, #0x2c6 00085f2f: 0F12 CMPL ACC, @0x12 00085f30: 6608 SB $C$L75, HI 00085f31: 764874B4 LCR Run_spindle4 00085f33: 761F02D1 MOVW DP, #0x2d1 00085f35: 2823028D MOV @0x23, #0x028d 00085f37: 6F1B SB $C$L77, UNC $C$L75: 00085f38: 761F02B3 MOVW DP, #0x2b3 00085f3a: 9213 MOV AL, @0x13 00085f3b: 6017 SB $C$L77, NEQ 00085f3c: 761F02D4 MOVW DP, #0x2d4 00085f3e: 9223 MOV AL, @0x23 00085f3f: 5201 CMPB AL, #0x1 00085f40: 6004 SB $C$L76, NEQ 00085f41: 9A7C MOVB AL, #0x7c 00085f42: 76489650 LCR blinky $C$L76: 00085f44: 7648994E LCR preTransmission 00085f46: 8F404B00 MOVL XAR5, #0x004b00 00085f48: D404 MOVB XAR4, #0x4 00085f49: A0A9 MOVL @ACC, XAR5 00085f4a: 76489869 LCR ModbusMaster_begin 00085f4c: 28A90C1B MOV @AL, #0x0c1b 00085f4e: 28A801F4 MOV @AH, #0x01f4 00085f50: 76489767 LCR ModbusMaster_writeSingleRegister $C$L77: 00085f52: 761F02D5 MOVW DP, #0x2d5 00085f54: 9202 MOV AL, @0x2 00085f55: 5201 CMPB AL, #0x1 00085f56: FFE1FF1A B -230, EQ 00085f58: FFEFFEC9 B -311, UNC Ecap_PinConf(): 00085f5a: FE02 ADDB SP, #2 00085f5b: 76807900 MOVL XAR6, #0x007900 00085f5d: D406 MOVB XAR4, #0x6 00085f5e: D58A MOVB XAR5, #0x8a 00085f5f: 06A6 MOVL ACC, @XAR6 00085f60: 76488B7E LCR XBAR_setInputPin 00085f62: FF2A4185 MOV ACC, #0x4185 << 10 00085f64: 7648881A LCR GPIO_setPinConfig 00085f66: 0201 MOVB ACC, #1 00085f67: 1E42 MOVL *-SP[2], ACC 00085f68: 028A MOVB ACC, #138 00085f69: 7648846D LCR GPIO_setPadConfig 00085f6b: D400 MOVB XAR4, #0x0 00085f6c: 028A MOVB ACC, #138 00085f6d: 764888ED LCR GPIO_setDirectionMode 00085f6f: D403 MOVB XAR4, #0x3 00085f70: 028A MOVB ACC, #138 00085f71: 764887E2 LCR GPIO_setQualificationMode 00085f73: 8F780401 MOVL XAR5, #0x380401 00085f75: 8F0882B5 MOVL XAR4, #0x0882b5 00085f77: A0A9 MOVL @ACC, XAR5 00085f78: 76489777 LCR Interrupt_register 00085f7a: 8F380401 MOVL XAR4, #0x380401 00085f7c: A8A9 MOVL @ACC, XAR4 00085f7d: 76488887 LCR Interrupt_enable 00085f7f: 76807900 MOVL XAR6, #0x007900 00085f81: D407 MOVB XAR4, #0x7 00085f82: D58E MOVB XAR5, #0x8e 00085f83: 06A6 MOVL ACC, @XAR6 00085f84: 76488B7E LCR XBAR_setInputPin 00085f86: FF2A4187 MOV ACC, #0x4187 << 10 00085f88: 7648881A LCR GPIO_setPinConfig 00085f8a: 0201 MOVB ACC, #1 00085f8b: 1E42 MOVL *-SP[2], ACC 00085f8c: 028E MOVB ACC, #142 00085f8d: 7648846D LCR GPIO_setPadConfig 00085f8f: D400 MOVB XAR4, #0x0 00085f90: 028E MOVB ACC, #142 00085f91: 764888ED LCR GPIO_setDirectionMode 00085f93: 028E MOVB ACC, #142 00085f94: D403 MOVB XAR4, #0x3 00085f95: 764887E2 LCR GPIO_setQualificationMode 00085f97: 8F790402 MOVL XAR5, #0x390402 00085f99: 8F08830E MOVL XAR4, #0x08830e 00085f9b: A0A9 MOVL @ACC, XAR5 00085f9c: 76489777 LCR Interrupt_register 00085f9e: 8F390402 MOVL XAR4, #0x390402 00085fa0: A8A9 MOVL @ACC, XAR4 00085fa1: 76488887 LCR Interrupt_enable 00085fa3: 76807900 MOVL XAR6, #0x007900 00085fa5: D408 MOVB XAR4, #0x8 00085fa6: D592 MOVB XAR5, #0x92 00085fa7: 06A6 MOVL ACC, @XAR6 00085fa8: 76488B7E LCR XBAR_setInputPin 00085faa: FF2A4201 MOV ACC, #0x4201 << 10 00085fac: 7648881A LCR GPIO_setPinConfig 00085fae: 0201 MOVB ACC, #1 00085faf: 1E42 MOVL *-SP[2], ACC 00085fb0: 0292 MOVB ACC, #146 00085fb1: 7648846D LCR GPIO_setPadConfig 00085fb3: D400 MOVB XAR4, #0x0 00085fb4: 0292 MOVB ACC, #146 00085fb5: 764888ED LCR GPIO_setDirectionMode 00085fb7: D403 MOVB XAR4, #0x3 00085fb8: 0292 MOVB ACC, #146 00085fb9: 764887E2 LCR GPIO_setQualificationMode 00085fbb: 8F7A0403 MOVL XAR5, #0x3a0403 00085fbd: 8F088367 MOVL XAR4, #0x088367 00085fbf: A0A9 MOVL @ACC, XAR5 00085fc0: 76489777 LCR Interrupt_register 00085fc2: 8F3A0403 MOVL XAR4, #0x3a0403 00085fc4: A8A9 MOVL @ACC, XAR4 00085fc5: 76488887 LCR Interrupt_enable 00085fc7: 76807900 MOVL XAR6, #0x007900 00085fc9: D409 MOVB XAR4, #0x9 00085fca: D596 MOVB XAR5, #0x96 00085fcb: 06A6 MOVL ACC, @XAR6 00085fcc: 76488B7E LCR XBAR_setInputPin 00085fce: FF2A4203 MOV ACC, #0x4203 << 10 00085fd0: 7648881A LCR GPIO_setPinConfig 00085fd2: 0201 MOVB ACC, #1 00085fd3: 1E42 MOVL *-SP[2], ACC 00085fd4: 0296 MOVB ACC, #150 00085fd5: 7648846D LCR GPIO_setPadConfig 00085fd7: D400 MOVB XAR4, #0x0 00085fd8: 0296 MOVB ACC, #150 00085fd9: 764888ED LCR GPIO_setDirectionMode 00085fdb: D403 MOVB XAR4, #0x3 00085fdc: 0296 MOVB ACC, #150 00085fdd: 764887E2 LCR GPIO_setQualificationMode 00085fdf: 8F7B0404 MOVL XAR5, #0x3b0404 00085fe1: 8F0883C0 MOVL XAR4, #0x0883c0 00085fe3: A0A9 MOVL @ACC, XAR5 00085fe4: 76489777 LCR Interrupt_register 00085fe6: 8F3B0404 MOVL XAR4, #0x3b0404 00085fe8: A8A9 MOVL @ACC, XAR4 00085fe9: 76488887 LCR Interrupt_enable 00085feb: 76484F3C LCR initECAP 00085fed: FE82 SUBB SP, #2 00085fee: 0006 LRETR Device_enableUnbondedGPIOPullups(): 00085fef: FE02 ADDB SP, #2 00085ff0: 8F05D008 MOVL XAR4, #0x05d008 00085ff2: 2901 CLRC SXM 00085ff3: 06C4 MOVL ACC, *+XAR4[0] 00085ff4: 18A90700 AND @AL, #0x0700 00085ff6: 9100 ANDB AH, #0x0 00085ff7: FF47 SFR ACC, 8 00085ff8: 9641 MOV *-SP[1], AL 00085ff9: 5206 CMPB AL, #0x6 00085ffa: 6004 SB $C$L13, NEQ 00085ffb: 76489392 LCR Device_enableUnbondedGPIOPullupsFor176Pin 00085ffd: 6F01 SB $C$L13, UNC $C$L13: 00085ffe: FE82 SUBB SP, #2 00085fff: 0006 LRETR 00086000: AABD MOVL *SP++, XAR2 00086001: 5AAD MOVZ AR2, @SP 00086002: DA84 SUBB XAR2, #4 00086003: FE42 ADDB SP, #66 00086004: 967F MOV *-SP[63], AL 00086005: 5200 CMPB AL, #0x0 00086006: 6003 SB 3, NEQ 00086007: 0E7F MOVU ACC, *-SP[63] 00086008: 6F02 SB 2, UNC 00086009: 0200 MOVB ACC, #0 0008600a: 1E76 MOVL *-SP[54], ACC 0008600b: 8F0700A8 MOVL XAR4, #0x0700a8 0008600d: FF3A LSL ACC, 11 0008600e: 560100A4 ADDL @XAR4, ACC 00086010: A878 MOVL *-SP[56], XAR4 00086011: 0200 MOVB ACC, #0 00086012: 1E7A MOVL *-SP[58], ACC 00086013: 1E7C MOVL *-SP[60], ACC 00086014: 1E7E MOVL *-SP[62], ACC 00086015: 2BF2 MOV *+XAR2[6], #0 00086016: 2BEA MOV *+XAR2[5], #0 00086017: 7622 EALLOW 00086018: 1E7E MOVL *-SP[62], ACC 00086019: 0218 MOVB ACC, #24 0008601a: 0F7E CMPL ACC, *-SP[62] 0008601b: 6914 SB 20, LOS 0008601c: 5CAD MOVZ AR4, @SP 0008601d: DCB4 SUBB XAR4, #52 0008601e: 5DA4 MOVZ AR5, @AR4 0008601f: 067E MOVL ACC, *-SP[62] 00086020: FF30 LSL ACC, 1 00086021: 560100A5 ADDL @XAR5, ACC 00086023: 067E MOVL ACC, *-SP[62] 00086024: FF30 LSL ACC, 1 00086025: 0778 ADDL ACC, *-SP[56] 00086026: 8AA9 MOVL XAR4, @ACC 00086027: 06C4 MOVL ACC, *+XAR4[0] 00086028: 1EC5 MOVL *+XAR5[0], ACC 00086029: 0201 MOVB ACC, #1 0008602a: 077E ADDL ACC, *-SP[62] 0008602b: 1E7E MOVL *-SP[62], ACC 0008602c: 0218 MOVB ACC, #24 0008602d: 0F7E CMPL ACC, *-SP[62] 0008602e: 66EE SB -18, HI 0008602f: 927F MOV AL, *-SP[63] 00086030: 5207 CMPB AL, #0x7 00086031: 6006 SB 6, NEQ 00086032: 761F0221 MOVW DP, #0x221 00086034: 920D MOV AL, @0xd 00086035: 96F2 MOV *+XAR2[6], AL 00086036: 6F05 SB 5, UNC 00086037: 761F0221 MOVW DP, #0x221 00086039: 920C MOV AL, @0xc 0008603a: 96F2 MOV *+XAR2[6], AL 0008603b: 92F2 MOV AL, *+XAR2[6] 0008603c: 9C01 ADDB AL, #1 0008603d: 560301A9 MOV ACC, @AL << 1 0008603f: 80A9 MOVZ AR7, @AL 00086040: BE00 MOVB XAR6, #0x00 00086041: 0E0E MOVU ACC, @0xe 00086042: C342 MOVL *-SP[2], XAR7 00086043: C244 MOVL *-SP[4], XAR6 00086044: 76408798 LCR 0x008798 00086046: 1E7A MOVL *-SP[58], ACC 00086047: 5CF2 MOVZ AR4, *+XAR2[6] 00086048: 761F0221 MOVW DP, #0x221 0008604a: DC01 ADDB XAR4, #1 0008604b: 80A4 MOVZ AR7, @AR4 0008604c: BE00 MOVB XAR6, #0x00 0008604d: 5603040E MOV ACC, @0xe << 4 0008604f: 0EA9 MOVU ACC, @AL 00086050: C342 MOVL *-SP[2], XAR7 00086051: C244 MOVL *-SP[4], XAR6 00086052: 76408798 LCR 0x008798 00086054: 1E7C MOVL *-SP[60], ACC 00086055: CC5E0FFF AND AL, *-SP[30], #0xfff 00086057: 0EA9 MOVU ACC, @AL 00086058: 0F7A CMPL ACC, *-SP[58] 00086059: 6705 SB 5, HIS 0008605a: 28EA01F8 MOV *+XAR2[5], #0x01f8 0008605c: FFEF026F B 623, UNC 0008605e: 5CAD MOVZ AR4, @SP 0008605f: 0216 MOVB ACC, #22 00086060: 1E42 MOVL *-SP[2], ACC ......... ...
After previous discussion we have changes done ,but it remains error same
Thanks&Regards
Ajay S
Ajay,
1) A sector can not be erased for more than 20K cycles. Your erase requirement seems to be very high. Since you are programming only 24 bytes each time, instead of erasing the sector after each program operation, you might want to program the next 24 bytes and access the latest data from the latest programmed address; and erase the sector only when the entire sector is used up. This way, you can reduce the erase cycles drastically and comply to be with in the 20K cycling specification.
2) Did you try to do a step execution to see which instruction caused the ITRAP error? Since you said that the issue occurs when executing the erase code, you can check whether or not the erase code is intact in RAM.
Thanks and regards,
Vamsi
Dear TI team,
1.As per reply, We understand that have to write 24byte data in sector6 and once the same data is updated then erase sector6 ,write the updated data in sector7 but we think it is also not reliable for our application.
2.We have not using software trap,when try to do the step execution error occurs with EEPROM ERASE function as discussed earlier.kindly help us to check how illegal ITRAP error occurs and resolve this issue.(we have no idea with it kindly guide us)
Thanks & Regards,
Ajay.s
Hi Ajay,
Are you available for a debug call early next week?
If yes, what are your convenient times/days? You can contact me on private chat like your colleagues did in the past.
Thanks and regards,
Vamsi
Hi vamsi,
yes,we are looking foward for debug call .we can connect on monday at your convenience time.
Thanks & Regards,
Ajay.S
Hi Ajay,
Please check my private message to you and continue chatting there.
Thanks and regards,
Vamsi
Hi Ajay,
I am not available tomorrow (Friday March 18th).
Hence, I need to move the meeting to early next week. Sorry about this.
Please check my private message and respond there (I am leaving this message here as well, so that you will check this and not wait for me).
Thanks and regards,
Vamsi
Thanks for your valuable time and support and our issue resolved ,closing our query..
Ajay,
Glad I am able to help and prove that it is not a CPU-hang issue.
Please stay with in the spec limit using the code suggestions that I provided to avoid flash-erase failure.
I am closing this post.
Thanks and regards,
Vamsi