TMS320F28377D: Other channels of the ADC affect the ADC sampling result

Julia,

Agree that this sounds the same as the memory cross-talk mentioned in the app note. 

1)Can you confirm with the customer that if the ACQPS is increased for the CH2 sample that we resolve back to 2029 even if sampling channel 5?

2)Can customer also try to insert the Ch 9 conversion in between the Ch5 and Ch2 and see if this also solves the issue?

I will need to check with some others on the team if there can exist any memory from odd to even. 

Best,

Matthew

Hi Matthew,

Thanks for your reply!

I found that I made a mistake in the previous statement, corrected as follows:

②if channel 5 is 2.3V, the sampling result of channel 2 is 2034;

In addition, if ACQPS is increased, this problem of customers can be solved.

For question 2), I will reply to you after confirming with the customer.

Best Regards,

Julia

Hi Matthew,

After sampling channel 5, the customer samples channel 9 again. The result is that the sampling value of channel 2 is not affected by channel 5. The settings are as follows:

In addition, after SOC0~4 is sampled, the next round of SOC0~4 sampling will be triggered after about 30us.

Best Regards,

Julia

Thanks Julia, let me talk to a few others on the team to see if they are aware of this.  I know that the wording in the DS is not exact, so perhaps there is some assumptions that we need to clarify for the customer.

Best,

Matthew

Wanted to also ask, can the customer share the trigger source/order from their code?  I want to make sure that the order really is Ch5 then Ch2, etc. 

Also I'm not sure if 30us will be too long for the rule to hold on even/odd. The S/H cap will start to settle to its steady state voltage which is likely not VREFLO after a bit of inactivity.

Best,

Matthew

Hi Matthew,

ADC A is triggered by EPWM at 30kHz. Other settings are as follows:

Best Regards,

Julia

Julia,

So the issue the customer is seeing is with the 2nd/3rd/4th/etc times through this loop i.e.the state in bold.

PWMTRIGGER -> ADCCH2->CH3->CH4->CH5->1/30kHz PWMTRIGGER->ADCCH2->CH3->CH4->CH5

I think there are 2 potential issues we need to address:

1)The first time through the loop from ADC IDLE, the value on the S/H cap will be unknown

2)The next times, even though we go from odd(5) ->even(2), there is some delay introduced by the PWMTRIGGER that the other channels do not see, i.e. CH2->CH3, CH3->CH4, etc.

I can look into this more with design, but I think due to both of these it would be safer option to either

a)increase the S/H window to better charge the cap, or

b)if time allows insert a sample of VREFLO at the beginning of the loop so that CH2 has a more known starting point of charge.

Let me know what you think.

Best,
Matthew

Hi Matthew,

Thank you for your reply! I will discuss this with the customer.

Best Regards,

Julia

Hi Matthew,

I have sent your answer back to the customer, they will try this method to solve the issue.

But the customer still say they need to know how the sampling capacitor discharges under 1) and 2). Can we have an explanation for this problem?

Many thanks!

Best Regards,

Julia

I will need to check with some of the other team members to get that info for those conditions.  Please give me a few days to respond.

Best,

Matthew

Hi Matthew,

Is there any updates about this case? Many thanks!

Best Regards,

Julia

Julia,

Let me check back with the design team, I had a question about the above to them to understand the mechanism better.

Best,

Matthew

Julia,

Can customer share the following:

1)Input RC network that the user has connected

2)VREF & VDDA supply voltage

Best,

Matthew

Hi Matthew,

1)Input RC network that the user has connected

442Ω/1nF

2)VREF & VDDA supply voltage

3.2V/3.3V

Best Regards,

Julia

Thanks Julia, let me share this with design team and get back to you.  Please give us until Monday end of day US time for our next update.

Best,

Matthew

Hi Julia,

Referring to the TRM section, “Choosing an Acquisition Window Duration” and the “Single-ended Input Model Parameters” in DS, we can approximate the minimum sample and hold times for the 442 Ω / 1nF external RC impedance in the customer’s application.  Using the  formula, time constant = (442 Ω + 425 Ω)*14.5pF + 442 Ω*(~6pF + 1nF) =  12.57ns + 444.65ns = 457.2ns.  I chose ~6pF for parasitic pin capacitance as this is the typical value for all the pins, except ADCINB0, per DS.  The number of time constants (assuming 0.5LSB settling)  k = ln(4096/0.5) – ln((1nF + 6pF)/14.5pF) = 9.01 – 4.24 = 4.77.  Sampling time should at least be equal to or greater than the product of time constant and the number of time constants, SH = 457.2ns*4.77 = 2.18uS.  You can already see that the SH used by the customer is not enough.  With 200MHz SYSCLK (5ns SYSCLK period), customer should be using an ACQPS of about 435 to meet an SH of 2.18uS.  If customer desires a shorter sampling time, general rule is to minimize the external RCs or to buffer the signal after the RC (and before feeding to ADC input) to increase the drive strength.

Regards,

Joseph

Hi Joseph,

Thanks for your reply.

You are right, customer can indeed solve this problem by increasing SH. Currently what customers want to know is why they have a memory cross-talk problem when they use an odd channel to an even channel, or an even channel to an odd channel. This is inconsistent with what our datasheet says. The customer wants to understand this discharge process, how the sampling capacitor discharges?

Best Regards,

Julia