Dear Sirs
My design goal is to have the TMS320F28004x be the SPI slave to another uC. The protocol is as follows; the TMS320F28004x will put out a 50us to 100us positive pulse to indicate that new data is available. The master SPI will then issue a CS and then start the SCK. There will be 40 bytes of data that can be transferred depending on the master clocking. The master will generate the necessary number of clocks pulses to get the data it wants. Therefore, if it wants only 4 bytes of data it will generate only 16 clock pulses and then remove the CS. I've looked at the "spi_ex4_external_loopback_fifo_interrupts" example. This seems like the approach I should take but I'm not sure. Are the FIFOs necessary? One question I have is I don't know how the interrupts are first generated. Is it when the Global Interrupt (INTM) and realtime interrupt (DBGM) are enabled and the FIFOs are empty? Which is the first interrupt, INT_SPIA_RX or INT_SPIB_TX? Thank you for your time.