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TMS320F280049C: SPI FIFO interrupt

Part Number: TMS320F280049C

Dear Sirs

My design goal is to have the TMS320F28004x be the SPI slave to another uC.  The protocol is as follows; the TMS320F28004x will put out a 50us to 100us positive pulse to indicate that new data is available.  The master SPI will then issue a CS and then start the SCK.  There will be 40 bytes of data that can be transferred depending on the master clocking.  The master will generate the necessary number of clocks pulses to get the data it wants.  Therefore, if it wants only 4 bytes of data it will generate only 16 clock pulses and then remove the CS.  I've looked at the "spi_ex4_external_loopback_fifo_interrupts" example.  This seems like the approach I should take but I'm not sure.  Are the FIFOs necessary?  One question I have is I don't know how the interrupts are first generated.  Is it when the Global Interrupt (INTM) and realtime interrupt (DBGM) are enabled and the FIFOs are empty?  Which is the first interrupt, INT_SPIA_RX or INT_SPIB_TX?  Thank you for your time.

  • Here is how spi_ex4_external_loopback_fifo_interrupts example is doing:

    SPIA - Configured as slave

    SPIB - Configured as master

    In the code, after the initial SPI configuration, SPIB FIFO interrupt is triggered (because TXFIFO is empty and TXFFST < 2) and spibTxFIFOISR routine does the transmission of data and SPIA FIFO interrupt is triggered as it receives data from SPIB (because RXFFST (2) = 2 (fifo threshold set). spiaRxFIFOISR routines is used to store the received contents in rData buffer.

    FIFO are useful in your case because you thinking of transmitting upto 40 bytes of data. I would recommend you to try executing the example code as it is and understand how the code works before you modify the code to suit your application.

    Regards,

    Manoj

  • Manoj

    Thank you for your advise.  I would like to keep this ticket open for a while until I'm comfortable with what is going on.  

  • You can re-open this ticket anytime you want by just replying to the thread.