TMS320F280049C: SPI slave CS and FIFO preloading

Dennis,

Dennis McGlumphy said:

My first question is, what happens to the slave SPI at the time the CS is disabled?  Will the slave SPI reset on its own?  What happens to the slave SPI TX FIFO?  Will it be flushed or will it remain as is?

When CS is pulled high from SPI master (controller), SPI(slave) will be put in high-impedance state. It however doesn't reset SPI module nor does it flush the SPI TX FIFO

Dennis McGlumphy said:

Second, in preparation to the master SPI asking for the data, how do I preload the slave SPI TX FIFO?  Thank you for your time. 

Answer depends upon your system requirement.

If what SPI slave needs to transmit is independent of what SPI master transmits then you can use TX FIFO interrupt to fill-up TX FIFO and keep it ready.

If SPI slave needs to transmit depends on what SPI master transmits, then SPI slave cannot preempt and fill the FIFO.

Regards,

Manoj

Dear Manoj

Thank you for your quick response.  

Manoj Santha Mohan said:

When CS is pulled high from SPI master (controller), SPI(slave) will be put in high-impedance state. It however doesn't reset SPI module nor does it flush the SPI TX FIFO

Then I must manually reset the slave SPI, flush the slave SPI TX FIFO and fill the slave SPI TX FIFO with new data.  How can I know when the CS has been disabled?  

Manoj Santha Mohan said:

Answer depends upon your system requirement.

If what SPI slave needs to transmit is independent of what SPI master transmits then you can use TX FIFO interrupt to fill-up TX FIFO and keep it ready.

How do I prefill the slave TX FIFO?  Do I use a SPI put or write function such as "SPI_writeDataNonBlocking(SPIA_BASE, sData[i]);"?  Should it be a blocking or nonblocking function?  

Dennis,

Dennis McGlumphy said:

Then I must manually reset the slave SPI, flush the slave SPI TX FIFO and fill the slave SPI TX FIFO with new data.  How can I know when the CS has been disabled?  

You can check the status of GPIO for CS to determine the status. If CS is activated, you can flush SPI TX FIFO manually and re-fill SPI TX FIFO with new data

Dennis McGlumphy said:

How do I prefill the slave TX FIFO?  Do I use a SPI put or write function such as "SPI_writeDataNonBlocking(SPIA_BASE, sData[i]);"?  Should it be a blocking or nonblocking function?

You can chose either blocking (or) non blocking  option. Both of them write to SPITXBUF register. Only difference is blocking option doesn't allow you to write if the SPI TX FIFO is full.

Regards,

Manoj

Dear Manoj

SPIA is a slave module.  For the moment, I'm not using the FIFO.  In registering my SPI interrupt, "Interrupt_register(INT_SPIA_RX, &spiaRxISR);" the "INT_SPIA_RX" interrupt vector is triggered by what?  Is it the receive buffer receiving a bit or being full.  Is it that the SPIA CS being asserted?  All interrupts are being enabled but I never enter the interrupt.  The CS for the slave, SPIA, is being manually applied by the master SPI from a TIVA launch pad.  I've looked at all four signals with a scope.  The clock, CS and TxData from the master all look as they should.  The RxData from the slave looks good but it's not the data that should be transmitted by the slave.  

Dennis,

When SPI slave receive data it should receive SPI RX interrupt and SPIINT will be set. Please check below table.

Regards,

Manoj