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Original question:

TMS320F28377S: use of DMA connection of the SPI hardware

TMS320F28379D: using DMA and SPI FIFO for multiple 24bit SPI slaves.

Miguel Angel Quero Corrales
Intellectual 410 points
Part Number: TMS320F28379D

Hello!

I find myself in a bit of a conundrum developing an interface to several LTC2344 quad 18bit ADC with SPI interface.

1. My first thought was that the ideal way to do so would be to use the DMA channels to handle to communication while I can do other things in the main CPU1. I saw a post by Juan Gamba, where he exemplifies how it could be achieved , but from what I am seeing these waiting loops are still happening withing the main loop, not really giving much sense to using the DMA, am I right?

2. Secondly, I also realized that the DMA limits the transmission data size to 16bits for SPI. Given that the ADC can transmit a continous stream of data of all the four channels in a 18bit+6bit(of configuration) per channel that would mean thatin total we receive 96 bits, which I understand could be handled by a burst of 6 16 bits in the receiveing channel of the, but it is quite a hassle for post-processing. Additionally, I would still be unsure how to deal with diferent slaves efficiently within the DMA. Any ideas?

On another note, I also consider just using the actual SPI modules and interrupts which can be configured for the right ammount of bits (2x12 bit transmission for each channel). Nevertheless, I am quite clueless as to how the actual interrupt process happens here. I have read through the Technical Reference Manual SPRUHM8I but it's not clear what generates the interrupts in SPI in FIFO mode. (E.g.  In FIFO mode, the SPI can interrupt the CPU upon a match condition between the current receive FIFO status (RXFFST) and the receive FIFO interrupt level (RXFFIL). If RXFFST is greater than or equal to RXFFIL, the receive FIFO interrupt flag (RXFFINT) will be set. SPIRXINT will be triggered in the PIE block if RXFFINT is set and the receive FIFO interrupt is enabled (RXFFIENA = 1).).

3.For RX, is the SPI module constantly receiving until it fills up the pile and then this generates an interrupt to check??

4.A similar description is provided for TX, but in an example code "Example_2837xDSpi_FFDLB_int.c" I see that the data is loaded SPITXBUF already in the ISR. What generates the interrupt in the first place?

5.Finally, what could be an efficient procedure here to handle the several bursts of info coming from each SPI slave ADC + the several slaves?

Best regards,

Miguel

  • 0
    TI__Mastermind 27871 points

    Hi Miguel,

    It's gonna be tricky interfacing the F28379D to the LTC2344. Some points below:

    It looks like the LTC2344 supports 1 to 4 output lanes. If you use a single lane, you could use a single SPI module on the F28379D. However, the max speed is 50MHz so you'll be limited on throughput.

    Using more than 1 lane would require using multiple SPI modules on the F28379D. There are only three SPI modules on the device, so you would be limited to 3 lanes max. You would need on to operate as a master and the other two to operate as slaves. There is a discussion on a similar topic on this thread.

    The VDDIO on the device is 3.3V, but the LTC only supports 1.8V and 5V I/O, so you will need a voltage translator. Not sure if you noticed that.

    The SPI module supports a maximum size 16-bit characters. I think you can work around this by using 8-bit character size and modify your code to generate three back-to-back 8-bit SPI transfers to generate the required 24 clocks.

    Employing DMA may be possible. The tricky part is the tCONV at the beginning of each transfer. You could use the CPU to toggle SPI_CS, then kick off a timer, which would trigger the DMA after X cycles (equivalent to tCONV). Upon the timer event, the DMA would simultaneously write data to the SPI (to force it to generate the necessary clocks) and read data from the SPI (to receive the data from the ADC). The number of bytes would depend on your lane configuration. For one lane, four channels, the DMA would write 3 bytes x 4 channels = 12 bytes and read 12 bytes.

    Before exploring the SPI/DMA configuration further, I would suggest you think about the speed and throughput limitations you will face and determine if you can still meet the requirements of your application.

  • 0 in reply to Gus Martinez
    Intellectual 410 points

    Hi Gus,

    Thanks so much for your inputs!! Very considerate of you =)

    So to respond to your points in order:

    I do plan on using a single lane (two slaves for each of the 3 SPI modules though). The max speed of 50MHz is way more than enough given I'm using these LTCs for a 200kHz AC/DC three phase synchronous rectifier.

    For the voltage on each side, I am actually using an LTM2886-5s with integrated DC/DC to have isolation between the "high-voltage" sensing side and the LV control side. The VL supplied in the LV side has been set to 5V, but it allows a max input threshold Voltage of 0.67 • VL which is 3.35V (I'm guessing this should be good enough?).

    Then for the technical side of the communications. My thought was to have the chip select and the CNV and BUSY signals independent of the actual SPI and only trigger the communications subject to the BUSY signals of each of the slaves. The one question that quickly pops to mind with your statements (three back-to-back 8-bit SPI transfers to generate the required 24 clocks // would simultaneously write data to the SPI (to force it to generate the necessary clocks)) is: is the CLK generated by the DSP only active during transmission? Do you think it would also be possible to just generate one transmission for softspan configuration in the whole setup (not even through DMA) and then just execute one DMA channel for the reception of SPI data for those 12 bytes continously (switching between slaves after each 12 byte reception)?

    Let me know your thoughts (this is my first time actually developing firmware =) ).

    Best regards,

    Miguel

  • 0 in reply to Miguel Angel Quero Corrales
    TI__Mastermind 27871 points

    Miguel,

    Miguel Angel Quero Corrales said:
    I do plan on using a single lane (two slaves for each of the 3 SPI modules though). The max speed of 50MHz is way more than enough given I'm using these LTCs for a 200kHz AC/DC three phase synchronous rectifier.

    OK, so each SPI would be connected to two slave ADCs and you will use separate chip select (CS) to enable one at a time? If so, just make sure the ADC tri-states its output pin when CS is is high such that you can tie the output pins of the two ADCs together.

    Miguel Angel Quero Corrales said:
    is the CLK generated by the DSP only active during transmission?

    Yes, you have to write something to the SPITXBUF register for the SPI to generate clocks. So when you read the 24-bits of each channel, you'll need to write dummy data to the SPITXBUF. As the SPI transmits data, it will simultaneously receive data.

    Miguel Angel Quero Corrales said:
    My thought was to have the chip select and the CNV and BUSY signals independent of the actual SPI and only trigger the communications subject to the BUSY signals of each of the slaves.

    Ah yes, that make sense.

    Miguel Angel Quero Corrales said:
    Do you think it would also be possible to just generate one transmission for softspan configuration in the whole setup (not even through DMA) and then just execute one DMA channel for the reception of SPI data for those 12 bytes continously (switching between slaves after each 12 byte reception)?

    Looking at the LTC data sheet, it looks like the LTC sends the CH0 conversion result during the transmission of the SoftSpan configuration. So I don't think it's possible to completely decouple the two. 

    I'd like to amend my previous statement. The DMA only works with 16-bit and 32-bit words. In this case it might be better to use 16-bit char size on the SPI. Your DMA TX channel can be setup to send a txbuf of size 16-bit x N (where N = 6, since four ADC channels x 24 bits / channel / 16 bits per word = 6). Similarly the RX channel can be set to receive an rxbuf of size 16-bit x N. The first 16-bit data in the txbuf can have the 12-bit SoftSpan config (just make sure the 12-bits are shifted to the top of the 16-bit word since the SPI will shift those out first) and the rest can be zeros. The LTC datasheet mentions the SDI line needs to be all zeros after SoftSpan for some reason (Figure 18). You can then have a txbuf and rxbuf for each SPI slave.

  • 0 in reply to Gus Martinez
    Intellectual 410 points

    Gus Martinez said:

    OK, so each SPI would be connected to two slave ADCs and you will use separate chip select (CS) to enable one at a time? If so, just make sure the ADC tri-states its output pin when CS is is high such that you can tie the output pins of the two ADCs together.



    That's a really good point. It seems when CS is disabled (high) the outputs are in Hi-Z so it should be fine.

    Gus Martinez said:

    Yes, you have to write something to the SPITXBUF register for the SPI to generate clocks. So when you read the 24-bits of each channel, you'll need to write dummy data to the SPITXBUF. As the SPI transmits data, it will simultaneously receive data.

    Looking at the LTC data sheet, it looks like the LTC sends the CH0 conversion result during the transmission of the SoftSpan configuration. So I don't think it's possible to completely decouple the two. 



    Having a further look under the Programming the SoftSpan Configuration Register in CMOS I/O Mode (Pg. 34), it seems something smart could be done which is to first configure the SoftSpan in a first transmission (the IC has the ability to hold that configuration unless changed), previously to enabling the DMA transmission and reception, and then configure the transmision (new config of the softstpan) to be all zeros for the duration of the whole transaction (which seems to be an exception in SoftSpan configuration as it also just allows retaining the previous configuration, what a wonder!).

    Gus Martinez said:

    I'd like to amend my previous statement. The DMA only works with 16-bit and 32-bit words. In this case it might be better to use 16-bit char size on the SPI. Your DMA TX channel can be setup to send a txbuf of size 16-bit x N (where N = 6, since four ADC channels x 24 bits / channel / 16 bits per word = 6). Similarly the RX channel can be set to receive an rxbuf of size 16-bit x N. The first 16-bit data in the txbuf can have the 12-bit SoftSpan config (just make sure the 12-bits are shifted to the top of the 16-bit word since the SPI will shift those out first) and the rest can be zeros. The LTC datasheet mentions the SDI line needs to be all zeros after SoftSpan for some reason (Figure 18). You can then have a txbuf and rxbuf for each SPI slave.



    Exactly what I was thinking. With the extra bit of info from the previous comment I think it should be viable, just a bit of rearanging the data received from the ADC.

    Thanks so much, and I will be updating the results asap, but I think this resolves my doubts for now.

    Cheers for such an efficient communication, best experience here so far!

    Miguel