TMS320F28379D: Why does Tx FIFO Status =16 in the DMA SPI Tx complete ISR when Rx/Tx burst sizes = 1 and Rx/Tx Fifo level = 1

Hello,

My application is transmitting and receiving variable length data over SPI using DMA. 

To do so, I configured the SPI and DMA as follows:

DMA

DMA Ch1 (high priority): SPI Tx, burst size =1, Transfer Size = length of data

DMA Ch2: SPI Rx, burst size = 1, Transfer Size = length of data

SPI

TXFFIL = 1, RXFFIL = 1

I noticed that the Tx FIFO Status =16 in the DMA SPI Tx complete ISR.  Why is the Tx FIFO getting filled up when the FIFO level and burst sizes are 1?

The reason I ask is that I was thinking about changing the Fifo levels and burst size to values greater than 1 and sending the last piece of data in the DMA SPI Tx complete ISR, however, that is not possible if the Tx Fifo is full.  I tried to get around the Tx Fifo full issue by enabling the SPI Tx Fifo interrupt in the DMA SPI Tx complete ISR, but the SPI Tx Fifo interrupt is never called.  I think it is not possible to use the Tx Fifo interrupt while using the DMA with the SPI.  Is that correct?

Update: I just noticed that I had changed the Burst size = 8, therefore, Tx FIFO Status =16 in the DMA SPI Tx complete ISR isn't that strange after all.  I will try to see if Fifo level = 4 and Burst size = 4 works better.